6 8 6 11 bit error rate simulated performance

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: nal Codes, Using Finite Interleaving with I=5 .......................... 6-8 6-11 Bit Error Rate Simulated Performance of the CCSDS Concatenated Scheme with Outer E=8 Reed-Solomon Code (255,239) and Inner Punctured Convolutional Codes, Using Finite Interleaving with I=5 .......................... 6-9 6-12 Word Error Rate Simulated Performance of the CCSDS Concatenated Scheme with Outer E=8 Reed-Solomon Code (255,239) and Inner Punctured Convolutional Codes, Using Finite Interleaving with I=5 .......................... 6-9 7-1 Example of Turbo Encoder/Decoder ............................................................................ 7-1 7-2 Block Diagram of Turbo Encoder ................................................................................ 7-2 7-3 Turbo Encoder Block Diagram..................................................................................... 7-3 7-4 Structure of the Turbo Decoder .................................................................................... 7-5 7-5 Basic Circuits to Implement the Log-APP Algorithm.................................................. 7-6 7-6 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes with Block Size 1784 Bits, Measured from JPL DSN Turbo Decoder, 10 Iterations .................................................................................................................. 7-8 7-7 BER & FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes with Block Size 3568 Bits, Software Simulation, 10 Iterations ................................... 7-8 7-8 BER & FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes with Block Size 7136 bits, Software Simulation, 10 Iterations.................................... 7-9 7-9 BER & FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes with Block Size 8920 Bits, Measured from JPL DSN Turbo Decoder, 10 Iterations .................................................................................................................. 7-9 7-10 BER & FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes, Block Size 16384 Bits, Software Simulation, 10 Iterations ....................................... 7-10 CCSDS 130.1-G-1 Page viii June 2006 TM SYNCHRONIZATION AND CHANNEL CODING —SUMMARY OF CONCEPT AND RATIONALE CONTENTS (continued) Figure Page 7-11 Illustration of Decoder Speedup Using Stopping Rules ............................................. 7-10 7-12 BER Performance of Turbo Codes Compared to Older CCSDS Codes (Except Cassini/Pathfinder Code: Reed-Solomon (255,223) + (15,1/6) Convolutional Code), Block Size 1784 Bits (Interleaving Depth = 1), Software Simulation, 10 Iterations ............................................................................. 7-12 7-13 BER Performance of Turbo Codes Compared to Older CCSDS Codes (Except Cassini/Pathfinder Code: Reed-Solomon (255,223) + (15,1/6) Convolutional Code), Block Size 8920 Bits (Interleaving Depth = 5), Software Simulation, 10 Iterations ............................................................................. 7-13 7-14 Illustration of Turbo Code Error Floor ....................................................................... 7-14 8-1 Block Diagram of the Recommended Pseudo-Randomizer ......................................... 8-2 8-2 Turbo Codeblock with Attached Sync Marker............................................................. 8-6 8-3 Turbo-CRC Encoder ..................................................................................................... 8-8 8-4 Block Diagrams for Implementing the (Optional) (a) ‘NRZ-L to NRZ-M Conversion’ and (b) Its Inverse .................................................................................. 8-10 C-1 Comparison of Turbo Code Performance with Blocklength-Constrained Lower Bound ................................................................................................................C-2 C-2 Performance Comparison for Pseudo-Random and Algorithmic Permutations...........C-4 C-3 Interpretation of Permutation........................................................................................C-4 Table 4-1 Puncturing Patterns for the CCSDS Punctured Convolutional Code Rates ................. 4-3 6-1 Frame Lengths for All Interleaving Depths.................................................................. 6-3 CCSDS 130.1-G-1 Page ix June 2006 TM SYNCHRONIZATION AND CHANNEL CODING —SUMMARY OF CONCEPT AND RATIONALE 1 1.1 DOCUMENT PURPOSE, SCOPE, AND ORGANIZATION PURPOSE This report contains the concept and supporting rationale for TM Synchronization and Channel Coding developed by the Consultative Committee for Space Data Systems (CCSDS). It has been prepared to serve two major purposes: a) to provide an introduction and overview for the Channel Coding concept upon which the detailed CCSDS TM Synchronization and Channel Coding specifications (reference [3]) are based; b) to describe and explain the codes considered and to supply the supporting rationale. Supporting perfor...
View Full Document

This document was uploaded on 03/06/2014.

Ask a homework question - tutors are online