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2 forward connection vector for both component codes

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Unformatted text preview: 3 shall be G1 = 11011. i) Puncturing of every other symbol from each component code shall be done for rate 1/2. ii) No puncturing shall be done for rate 1/3. CCSDS 131.0-B-2 Page 6-5 August 2011 CCSDS RECOMMENDED STANDARD FOR TM SYNCHRONIZATION AND CHANNEL CODING – Forward connection vectors for rate 1/4 shall be G2 = 10101, G3 = 11111 (1st component code); G1 = 11011 (2nd component code). No puncturing is done for rate 1/4. 3) Forward connection vectors for rate 1/6 shall be G1 = 11011, G2 = 10101, G3 = 11111 (1st component code); G1 = 11011, G3 = 11111 (2nd component code). No puncturing shall done for rate 1/6. i) Turbo encoder operation: 1) Each input frame of k information bits shall be held in a frame buffer, and the bits in the buffer shall be read out in two different orders for the two component encoders. 2) The first component encoder (a in figure 6-2) shall operate on the bits in unpermuted order (‘in a’), while the second component encoder (b figure 6-2) shall receive the same bits permuted by the interleaver (‘in b’). NOTES 1 The read-out addressing for ‘in a’ is a simple counter, while the addressing for ‘in b’ is specified by the Turbo code permutation described in 6.3g). 2 The recommended encoder block diagram is shown in figure 6-2. 3 The component encoders are recursive convolutional encoders realized by feedback shift registers as shown in figure 6-2. The circuits shown in this figure implement the backward connection vector, G0, and the forward connection vectors, G1, G2, G3, specified in 6.3h). A key difference between these convolutional component encoders and the standalone convolutional encoder recommended in section 3 is their recursiveness. In the figure this is indicated by the signal (corresponding to the backward connection vector G0) fed back into the leftmost adder of each component encoder. j) Turbo Codeword specification: 1) Both component encoders (see figure 6-2) shall be initialized with ‘0’s in all registers, and both shall run for a total of k+4 bit times, producing an output Codeword of (k+4)/r encoded symbols, where r is the nominal code rate. 2) For the first k bit times, the input switches shall...
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