Bcdcount library ieee use ieeestdlogic1164all use

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Unformatted text preview: END LOOP; Jim Duckworth, WPI 7 The Process Statement - Module 4 Process example - BCD_COUNT LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; -- required for addition ENTITY bcd_count IS -- bcd counter PORT (clk, reset: IN std_logic; q : OUT std_logic_vector (3 DOWNTO 0)); END bcd_count; Jim Duckworth, WPI 8 The Process Statement - Module 4 BCD_COUNT (cont’d) ARCHITECTURE behav OF bcd_count IS SIGNAL temp : std_logic_vector (3 DOWNTO 0); BEGIN -- two concurrent statements (Process and signal assignment) PROCESS (clk, reset) -- sensitivity list for process BEGIN IF reset = ‘1’ THEN temp <= “0000”; ELSIF clk’EVENT AND clk = ‘1’ THEN IF temp = “1001” THEN -- check if ‘9’ temp <= “0000”; -- back to ‘0’ ELSE temp <= temp + 1; -- increment by one END IF; END IF; END PROCESS; q <= temp; END behav; Jim Duckworth, WPI 9 The Process Statement - Module 4 Synthesis Results Jim Duckworth, WPI 10 The Process Statement - Module 4 RTL and Technology Schematic Jim Duckworth, WPI 11 The Process Statement - Module 4 Variable Assignment • Assigns a new value (immediately) to a variable a := b + 45; -- a and b are integers • Variables only used in process or subprograms – Declared inside process – Not accessible outside of process – Need to assign to signal for access outside process • Used for temporary storage Jim Duckworth,...
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