Combinational logic in combinational logic the

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Unformatted text preview: Jim Duckworth, WPI 21 The Process Statement - Module 4 Process Overview • A process may be used to describe combinational or sequential (clocked) logic. – Combinational Logic • in combinational logic the outputs are only dependent on the inputs • no latches or flip-flops should be generated – Sequential Logic • contains memory elements (storage) - outputs dependent on both current inputs and past events – see next module for examples Jim Duckworth, WPI 22 The Process Statement - Module 4 Process Style for Combinational Logic • General Rules – sensitivity list is required and MUST include all signals used in process • Synthesis tools will only provide warning, simulation will fail – variables must NOT be used before being set – last successive assignment to a signal is last one implemented – all outputs should have default values • if not, a latch will be generated to hold the current value – No WAIT statements allowed in process Jim Duckworth, WPI 23 The Process Statement - Module 4 Incorrect Combinational Process Jim Duckworth, WPI 24 The Process Statement - Module 4 Latch and constant value generated Jim Duckworth, WPI 25 The Process Statement - Module 4 Incorrect Process for Combinational Logic ENTITY comparator IS -- 4-bit magnitude comparator PORT(a,b : IN std_logic_vector(3 DOWNTO 0); equal, less, great : OUT std_logic); END comparator; ARCHI...
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This document was uploaded on 03/06/2014.

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