C stdlogic begin b a order does not matter d c c

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Unformatted text preview: - Module 4 Concurrent Signals - Reminder ENTITY test3 IS PORT (a , clk d END test3; : IN std_logic; : OUT std_logic); ARCHITECTURE arch OF test3 IS SIGNAL b, c : std_logic; BEGIN b <= a; -- order does not matter d <= c; c <= b; END arch; Jim Duckworth, WPI 16 The Process Statement - Module 4 Synthesis Results Jim Duckworth, WPI 17 The Process Statement - Module 4 RTL Schematic Jim Duckworth, WPI 18 The Process Statement - Module 4 Signals in Clocked Process (flip-flops) ENTITY test3a IS PORT (a , clk : IN std_logic; d : OUT std_logic); END test3a; ARCHITECTURE arch OF test3a IS SIGNAL b, c : std_logic; BEGIN PROCESS (clk) BEGIN IF clk'EVENT AND clk = '1' THEN b <= a; c <= b; d <= c; END IF; END PROCESS; -- b, c, d updated with previous values of a, b, c END arch; Jim Duckworth, WPI 19 The Process Statement - Module 4 Synthesis Results Jim Duckworth, WPI 20 The Process Statement - Module 4 RTL Schematic...
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This document was uploaded on 03/06/2014.

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