Example2 architecture arch of example2 is begin

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Unformatted text preview: WPI 12 The Process Statement - Module 4 Example ENTITY example2 IS -PORT(a_bus : IN integer RANGE 0 TO 127; flag : OUT std_logic); END example2; ARCHITECTURE arch OF example2 IS BEGIN PROCESS(a_bus) VARIABLE j : integer RANGE 0 to 127; --only visible in process BEGIN j := a_bus / 2; j := j + 4; -- update immediately IF j > 50 THEN flag <= '1'; ELSE flag <= '0'; END IF; END PROCESS; END arch; Jim Duckworth, WPI 13 The Process Statement - Module 4 Signal Assignments inside a Process • Changes the value of a signal (wire or net) • (If outside a process then it is a concurrent statement) • If inside a process then executed sequentially with other statements. • A signal assignment will supersede a previous assignment to the same signal • A signal update occurs after a delta delay (very small delay) - allows for ordering of events. • Very important difference: – variables updated immediately – signals get new values at a later time (usually end of process or when simulation time advances) Jim Duckworth, WPI 14 The Process Statement - Module 4 Example ARCHITECTURE behav OF incorrect_example IS SIGNAL a : integer; -- declare internal signal BEGIN PROCESS(f) VARIABLE j, k : integer; BEGIN j := f + k; -- j updated immediately a <= j + 1; -- a updated at end of process k := a; -- k gets old value of a END PROCESS END behav; Jim Duckworth, WPI 15 The Process Statement...
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This document was uploaded on 03/06/2014.

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