Lec11-Shared memory architecture and programming

Lec11-Shared memory architecture and programming - Lecture...

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Lecture 11 Shared memory: Architecture and programming
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 2 Announcements • Datastar accounts • UPC lecture next week
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 3 Shared memory architecture • Every processor has direct access to all of memory • The address space is global to all processors • Hardware automatically performs the global to local mapping using virtual to physical address translation
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 4 Two kinds of shared memory architectures • Distinguished by whether or not memory access time is uniform UMA : Uniform Memory Access time – In the absence of contention, all processors see the same access time to memory (approximates a PRAM) – Also called a Symmetric Multiprocessor (SMP) – Usually bus based: not a scalable solution NUMA : Non-Uniform Memory Access time – Memory access time depends on distance to memory – Also called Distributed Shared Memory (DSM) – Elaborate interconnect structure
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 5 Cache Coherence • A central design issue in shared memory architectures • Processors may read and write the same cached memory location • If one processor writes to the location, all others must eventually see the write X:=1 Memory
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 6 Cache Coherence • P1 & P2 load X from main memory into cache • P1 stores 2 into X • The memory system doesn’t have a coherent value for X X:=1 Memory P2 X:=1 P1 X:=1 X:=2
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 7 Cache Coherence Protocols • Ensure that all processors eventually see the same value • Two policies – Update-on-write (implies a write-through cache) – Invalidate-on-write X:=2 Memory P2 P1 X:=2 X:=2 X:=2
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 8 SMP architectures • Employ a snooping protocol to ensure coherence • Processors listen to bus activity I/O devices Mem P 1 $ Bus snoop $ P n Cache-memory transaction Parallel Computer Architecture , Culler, Singh, Gupta
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 9 Memory consistency and correctness • Cache coherence tells us that memory will eventually be consistent • The memory consistency policy tells us when this will happen • Even if memory is consistent, changes don’t propagate instantaneously • These give rise to correctness issues involving program behavior
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 10 Memory consistency • A memory system is consistent if the following 3 conditions hold – Program order – Definition of a coherent view of memory – Serialization of writes
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10/26/06 Scott B. Baden/CSE 260/Fall 2006 11 Program order • If a processor writes and then reads the same
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This note was uploaded on 02/20/2008 for the course CSE 260 taught by Professor Baden during the Fall '06 term at UCSD.

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Lec11-Shared memory architecture and programming - Lecture...

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