COM SCI 151 Fall - 1998 Midterm Exam

COM SCI 151 Fall - 1998 Midterm Exam - CSlBlB Midterm Exam...

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Unformatted text preview: CSlBlB Midterm Exam tag/{00 (Note: this is a closed book exam) Prof.: Leon Alkalai Fall ’96 — 11/06/96 Name: _ ____._—...~___-__._.___ SID: l) (10) You were the lead designer of a processor, call it Phase, a load/store machine like the MIPS machine we studied in class. Phase runs with a clock rate of 50MHZ and measurements showed the following instruction mix: CPI Operation Frequency ALU 47% l 12% 2 19% 2 Stores Branches Let’s assume that 25% of the ALU operations use one of the operands loaded directly from main memory and used only once. So, we propose adding ALU instructions that have one source operand in memory. The new register-memory instructions have CPI of 3. As a side effect of this change, the CPI for branch instructions is increased by one, but the clock rate remains the same. Call this new processor Pnew. a) What is the CPI for processors Phase and Pnew 15?, A Mu .9}: “354/. (P? “Slug nu f 313420 1 -( ‘ J Jr La uL. t; ion/l gallx gist/17.7.2!» Ml» lord-4 » 9 5mm; wt 0'} (is At (J L H 7‘3? 4. Z ' here «in on Mt cf(--3 7 - o M. It ((75 / 50 £9an __ {a 2 57“ a (\A J I fr- il/ r ‘ II ‘ u - i‘ 7‘ 1 (a? xfldwmwwzxzwm WWW»: m bn‘; _ / / I ’J _ (egg : .ufix’a’hfiSZb/FIFJZAS *-|2’2*,1‘7*3\, Pg 'Ll.9@ inle _ "—Mi _ - Name: SID: ‘ b) Would this change improve CPU performance (CPU time)? (0/0 No S] nu: TR (km/k “(J1 )3 h‘ M; a LHL”, 6P3 “W19! MI”!— W V14,” SL‘WC/ SID: _ Name: ‘2) (10) Suppose you work on a company and you have to buy a new computer. You are considering two options: machines A and B. Your workload is 1/0 bound, i.e., in machine A the CPU is used 40% of the time and the rest of the time the CPU waits for I/O. Furthermore, machines A and B are different in that the CPU for machine B is 5 times faster and 5 times more expensive than the CPU in machine A. Thefllin‘system is the same in both machines and it costs the sameas the CPU in machine A. (Assume that the cost of a machine is defined by CPU and I/O cost only). Given that the cost-effectiveness of a system is defined to be the ratio of performance divided by cost, which machine is more cost—effective? Show your work! (Hint: Performance here can be taken to be the time for a machine to run the workload, i.e., the time spent doing CPU work and the time spent doing I/O.) ' ‘9“ : Pf" +7 CPU“ ] (4251' of bnféT-Em 4;; CW”- W’ " 29» pg fl 1'- f¢u4 :4 7?; f/o : 6* PA I (1317- if c . fl? Wit" 0,, r _ I “I \. Pu haw. a. 1 {.HH NJ ' “M / “" “’”‘ w W" ‘5 min. i H , 1/0 =15 tr " I .‘71‘ 4 to; ?t""i€""“’l"‘fi ALP/HR " it 5?ny A A EAK 5.0! r a . 4 -. ; is I, A i I T M fibri- D( r Mrs "3) Y¢,'.A."‘- ‘6 #1,; «r a; ! {1,64% f Pas .' Doc? 1’ + ifg ' — WM A i ‘3 {Amt—"V1,, Qh' 3:; C C’TT 7C L( (M “F l x ' \ / \w ,i’ \‘a V3 771 Coi'i o'é $7M {3, Mai 0" '7 j I ,x l ,2 "3 3‘0 “0/ m n ,/ Name: fl 4 SID: _ 3) (15) Consider the following fragment of a C code which consists of a procedure call INCREMENT with two parameters: VECTOR, and SIZE, and performs the integer increment operation on each element of the vector: INCREMENT (int VECTOR, int SIZE) { int i; for(i=0;i<SIZE;i=i+1) VECTUREi] = VECTUREi] + 1; I ‘ a) Assume that the vector address is found in registerifi, the paramter SIZE is in register 6W0) $3, and i_is stored in register $49,. Using the MIPS instruction set, write the complete code for the C procedure call. Rember that the MIPS architecture uses a byte address. ‘ l {Ndeimzrnft‘t MAE $1 x i0! a” mom”!- ¢r(5di (“in i" 5’75)‘ 6-7”) 1’ L1,?! I. l W filogiflr- O ‘ I ‘ (R f; \I‘QICLU‘E‘ UCLTJ‘REEE" Lace-z 51+ Hf Mo, W1 it edit ‘H" " {617‘ b5? éjf icy/DOA“;— {t “(I {110 [+14% (Kiigyi 5L; r—Jc‘rr 69M Null, {3 $10 :2. r 70* W4 M‘v'rm «27+: M’s/m “J Add 4% 3C5/ $3 “‘1‘ oapd/c‘atu oi Ufa—ugh] a )n 5’71 ‘LV J5 afisq) x: Veda/fa) 3- 1-4 my ts WL $0,] =5 ‘I'lcrztn-‘A/fi— Vfid'orCL) 51o as, em) r am Mr (a mum" “*7 Mali 40/50, r 4: g: 2*! '3 Lot)? ____ _“J$J 961—5 Lou)? DDNE f f If“ Tu caJfi “Wk”! Latka {asyrs'h/fi M4 +6.0“. ) 65: (1J5 .C the \aae was " H'Qrsur—F‘MCWO (1's) Name: 7 4“ SID: _ 1—— b) Assume that every memory a ess instructio .,kes 2 c cles and every register oper- Or the procedure ation takes 1 cycle. For a. vector sfze of 100, c call for a CPU that executes at a clock rate of 100 MHz. : I Q l‘pLfl/[A’V( (Fur—'7 {WM 014 [C : Z/K f : Z (04C. I!” fit [00? = ’cvcchX/oo ; [/oa {MT 1/ MN“) i" ffié‘fp 5‘“. 9M («51 "fin-u. +3 (Jack I 7 2 H m“; 0% 5 (Ir) ' _ W *7 .3 ’ "’r°‘{*==‘w’>t :ch/aéjmd W4 m Name:__ - .._ SID: 4) (25) We wish to add the instruction incaje (increment and jump on equal) to the multicycle data path of the MIPS machine reproduced on the next page. This instruction has the format: incaje Rs, Rt, L1: m 6 16 This instruction 1W and branches to L1 the new Rt equals Rs, i.e., Rt 2 Rt + 1; if (Rs==Rt) goto L1; .. (a) Using the figure in the next page, show all the necessary modifications to the data (5/5) . . . . . . . . path and control lines needed to implement this instruction. Choose a solution that mini— mizes the number of clock cycles. (b) Show the steps in executing the incaje instruction in the multiclock data path using the same breakdown of steps we used in the book. Q n4 3,157, {4a “A “PC: ;-qc.am,cyr (706k - | as fl, “‘1'le fiwl +20") “(Jest olCUJ’lC LI 3. if Docs (rig-veg? AM -— .riysrwtme-réj ‘ rPC“; 31mm: rdclfthTSL'ZGYE’Sl-Zro jig-0'1] or Go 5&75 aL‘L‘l' il Clu-nfllra’ +0 in S‘lcfizz \ 3. Ala [LOP l$ rL #{wouvfivwifd— (+4», ‘[ Raj Lrtz {Aw-~17 4- tt“ “‘5’”! s {F(:+==‘3) Pcefl""’L v15 1421 .73.; it. «erases .3 F: :5“ .33 fid, Gfl 5v.1”? link?» 3 L mafia)» «wii 5 Q \fiaxfraéwi. vw EW& $5? 1.?wa g t3 2 .45 \a x a: n Ban 2E5 fine 3:: not“! guts-5 :Tm: €2.25“... .223. 0E3 log-30¢ a Sine. can". .013. 5:25“:— 3923 St; min—Eu: SID: _____. Emlsfl c3552. n Bani! 35.50 «52.8% I 3 as i i :3. ._. 50 EUmEZUa 350m"! 3:3“! Name: J— Name: __.__.a.~fi____....;L (c) Show the additions to the finite state machine of the figure below to implement the incaje instruction. (2H0) rnstruction decode/ Register fetch instruction fetcrt MemRead ALUSeIA=0 IorD=0 ALUSeiA=O IRWrite ALUSeIB=ll Start ALUSe|B=Oi ALUOD=OO ALUOp=OO . Pcwme Targethte PC Sou rce=OO Branch compietlon Memory address computation completion ALUSeiA=l ALUSe|B=00 ALUOp=01 PCWriteCond PCSource=01 ALUSelA=1 ALUSeIB=00 ALUOD=10 ALUSelA=1 ALUSeiB=10 ALUOp=00 PCSource=10 Memory access R-tyoe completion ALUSeIA=1 MemRead MemWrite ALUSeIA=1 ALUSeIA=1 RegDstél lorD=1 lor0=1 Regwr'te ALUSe|B=10 ALUSeIB=1O MemtORes=0 ALUOp=OO ALUOp=OO ALUSe'B=00 ALUOp=1O Write-back step MemRead ALUSeIA=1 IorD=1 RegWrite MemtoReg=1 Reg05t=0 ALUSe|B=1O ALUOp=00 ALu 54A :mlo “LI-4:46:00 AU‘AeF '3 15-1-00 "panic Win!“ = 9 “7°51” so wwtflfl-ZS W70? Name: _ I '_ SID: 5) (25) Consider the following three types of caches: a direct mapped, 2-way set as— sociative cache, and a fully associative cache, where each cache has a total of 8 l-word blocks‘ a) Using illustrations or table, show how the words in memory from location 0 to 31 map into the three different caches. Clearly number the blocks in the cache, and indicate the mapping policy for each cache. ‘r> DFrrLk “'1wa r fimmT. I L a wad YFC‘dxké l5 (cycle) 44.70"“ so W a} M word‘scs‘n W1stch l” ‘ Cat-L4. Llecflt ushc) (IR/ll) “15 M “5”” 0 l 2 3 ‘--/ ‘- I'L l 7 . B “I ‘ fa ' M Q. J's" 5M ,3 2‘3- ‘ 1/ lg, .r'? \t m m ?= P {75' ' 11m 7a "He. 77 "as 7‘? g 31' i r t g' l v N (Atw’c 3th: 0 l l Z 3 l/ g (3 7 (2‘) Zia/6L7 30l— 45504 - View. arc, 'Z. Slad‘ts l4 (4&5 50’. 5""? 915» M 1—1/1 7 ""”""’t 5/ 17-h” “Tr-L {7/ . TLL ward g 9L1. lm-lr; 61 gell‘f, M ram. 70 (at (hub... 61:7 Tu Wade bledrs (hf/M WES D r g 3. ‘/ Li S’ L: 7 g ‘1 {1’ H 1.5—. $4 (\i {b \1 =8 r? fit 77 7.7 1'0 , ,u 1 N If 7 a?“ 3'0 <7? 4.”— cao-H? set— . p f f: l 3 (/eee’“ 5) Afifacialh-‘C - TM. Woman] (/‘O'H’l5 (cm 5; ,7; V7 Mac/It, 5a a «flask Lt \/ (Ame “W- "71¢...MW554‘319J‘9' WW h - up RP» 4“ Wth A” Name: - :-_._ SID: b) Consider the cache mapping schemes of item a), and for the memory reference pattern shown in the table below, indicate for each of the three types of caches, whether each memory reference results in a cache hit or miss. Assume that the cache is initially empty and that we use the LRU replacement policy. Clearly show each case. c) Using the cache hit and miss penalties and cache hit ratios shown in the table below, calculate the average memory access time for each of the three cache types, using the hit and miss rates determined under Assume further that the three caches considered are write-back caches, with 35% of the cache blocks being dirty. (9/0) - 97% 99% t, = rt} + (who1 M3ng 4 7515i. 4 {l' LEM (3M ’ tr‘f' “infilW’tMl‘ {0 + [.05\j:,SS/QE?+ £00] "-1 @217 5/47 2-‘~“7 \1+{,03)L3V’93)*r0fl‘ \éfiSn F A. L 1‘; 4 (lomi'ggagDHOD‘j: th3gns 10 Name: SID: .-._ 6 ’L 6) (1.5) Assume a 32bit, byte address MIPS architecture, and a cache of size 2” 1-word blocks. For a direct mapped cache, 4-way set associative cache, and a fully associative cache, do the following: a) Calculate the total number of bits in each type of cache, inclhldi?g mtag bits7 data ‘il- 5‘? U“ " bits, and valid bits. V {fa-Lg: rz" Lwowt Mk5 IIJ élf J duh “I 3 Wm {3...r {. 6L LioLiL A4614 7:)“ " l.‘!' ° 11 Name: ”_ i L____ SID: ;. “i5 b) For the case of a 64KB (of data) cache, show the complete design for a direct memory cache, 4-way set associative cache, and a fully associative cache. Clearly indicate the tag parts, the cache index, and clearly indicate how ca e 1111 nd hi are determined for each case of the three cache types. (th we W k '5 EM (9/613 ...
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This test prep was uploaded on 02/21/2008 for the course CS 151 taught by Professor Alkalai during the Fall '98 term at UCLA.

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COM SCI 151 Fall - 1998 Midterm Exam - CSlBlB Midterm Exam...

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