Unformatted text preview: 6-bit AU Copyrigh C55x Data Computation Unit (DU)
00_0000 MAC MAC
CB External DB FF_FFF
F D-Unit executes most
mathematical operations AC0
Shift 40-bit Viterbi Hardware
DU Now, what happens to the result?... IEE, Slide 22 Copyrigh C55x Writes (E and F buses)
00_0000 EAB Internal AU FAB DU
AC3 32-bit write in one cycle IEE, Slide 23 Copyrigh Focus on C55x Architecture IEE, Slide 24 Copyrigh Functional Diagram of C5510 1 of 2
Functional IEE, Slide 25 Copyrigh Functional Diagram of C5510 2 of 2
Functional IEE, Slide 26 Copyrigh Pipelines of the C55x
There are 2 independent pipelines:
Program fetch pipeline (3 clock cycles)
Program execution pipeline (7 clock cycles) IEE, Slide 27 Pipeline execution breaks an operation into smaller
pieces that can be executed independently.
The fetch pipeline is done inside the Instruction
Buffer Unit and fills IBQ
The execute pipeline fetches instructions from IBQ
and executes them
and Copyrigh C55x Fetch Packet Pipeline
PF1 - gen prog address
PF2 - memory wait
F - fetch 4-byte packet PF1 PF2 F
PF1 PF2 F
PF1 PF2 F IBQ
4 bytes 64x8 Fetch-packet pipeline fetches 4-byte packets from program
memory INTO the IBQ every cycle (unless IBQ is full) Fetch packet pipeline operates independently from execute pipeline
Program Bus E Data Read Buses (B,C,D)
Data Write Buses (E,F) IEE, Slide 28 Copyrigh C55x Execute Pipeline
D AD AC1AC2 R D - decode opcode
AD - compute address
AC1 - gen read address
AC2 - memory wait
R - read operands
X - execute
W - write to memory D AD AC1AC2 R XW D AD AC1AC2 R IBQ
64x8 XW D AD AC1AC2 R
bytes E Data Read Buses (B,C,D)
Data Write Buses (E,F) XW D AD AC1AC2 R XW D AD AC1AC2 R XW D AD AC1AC2 R XW Execute pipeline fetches instructions
FROM the IBQ, then executes them
IU performs fetch/decode from IBQ AU generates operand addresses AU/DU execute instructions X: result to register
W: result to memory IEE, Slide 29 XW Copyrigh Execute Pipeline Phases 1 of 2
Read six bytes from the instruction buffer queue.
Decode an instruction pair or a single instruction.
Dispatch instructions to the appropriate CPU functional units.
Read STx_55 bits associated with data address generation:
ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC) AD
Read/modify registers involved in data address generation.
Perform operations that use the A-unit ALU.
Decrement ARx for the conditional branch instruction
Evaluate the condition of the XCC instruction AC1
Memory read operations, send addresses on the appropriate CPU
address IEE, Slide 30 Copyrigh Execute Pipeline Phases 2 of 2
Allows one cycle for memories to respond to read requests. R
Read data from memory, I/O space, and MMR-addressed registers.
Read A-unit registers
Evaluate the conditions of conditional instructions. X
Read/modify registers that are not MMR-addressed.
Read/modify individual register bits.
Evaluate the condition of the RPTCC instruction.
Write data to MMR-addressed registers or to I/O space (peripheral
Write data to memory.
IEE, Slide 31 Copyrigh Program
00_0000 C5510 Unified Memory Map
Data 00_0000 MMRs 00_00C0 DARAM (32KW) 00_0060 01_0000 00_8000 Internal SARAM (128KW) 05_0000 02_8000 External
A(24) IEE, Slide 32 Program and data share
the same map
2 ways to view the map:
Data 23 0 23 10 0 1. Program - (Bytes)
core - 16M x 8-bit, linear 24-bit
- Used by fetch/decode logic
2. Data (Words)
- 8M x 16-bit, segmented into
64K pages, 23-bit address
- Most code written by a user
will access data Copyrigh Memory Access IEE, Slide 33 16M bytes of memory are addressable as
program space or data space
When the CPU uses program space to read
program code from memory, it uses 24-bit
addresses to reference bytes.
When program accesses data space, it uses 23-bit
addresses to reference 16-bit words.
In both cases, the address buses carry 24-bit
values, but during a data-space access, the least
significant bit on the address bus is forced to 0.
significant Copyrigh Data Memory
Data space is divided into 128 main data pages (0
through 127) of 64K addresses each.
An instruction that references a main data page
concatenates a 7-bit main data page value with a 16-bit
On data page 0, the first 96 addres...
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- Spring '14
- Central processing unit, X86, Processor register, Interrupt