iee slide 21 arau a d d r g e n x ar0 7 ar0 7 x cdp

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Unformatted text preview: 6-bit AU Copyrigh C55x Data Computation Unit (DU) 00_0000 MAC MAC Internal BB[16] CB[16] External DB[16] FF_FFF F D-Unit executes most mathematical operations AC0 AC1 AC2 AC3 40-bit ALU Shift 40-bit Viterbi Hardware Transition Regs Bit Operations DU Now, what happens to the result?... IEE, Slide 22 Copyrigh C55x Writes (E and F buses) 00_0000 EAB[24] Internal AU FAB[24] DU External EB[16] FB[16] FF_FFF F AC0 AC1 AC2 AC3 32-bit write in one cycle IEE, Slide 23 Copyrigh Focus on C55x Architecture IEE, Slide 24 Copyrigh Functional Diagram of C5510 1 of 2 Functional IEE, Slide 25 Copyrigh Functional Diagram of C5510 2 of 2 Functional IEE, Slide 26 Copyrigh Pipelines of the C55x There are 2 independent pipelines: Program fetch pipeline (3 clock cycles) Program execution pipeline (7 clock cycles) IEE, Slide 27 Pipeline execution breaks an operation into smaller Pipeline pieces that can be executed independently. pieces The fetch pipeline is done inside the Instruction The Buffer Unit and fills IBQ The execute pipeline fetches instructions from IBQ The and executes them and Copyrigh C55x Fetch Packet Pipeline C55x Fetch PF1 - gen prog address gen PF2 - memory wait PF2 F - fetch 4-byte packet PF1 PF2 F PF1 PF2 F PF1 PF2 F IBQ 4 bytes 64x8 Fetch-packet pipeline fetches 4-byte packets from program Fetch-packet 4-byte memory INTO the IBQ every cycle (unless IBQ is full) Fetch packet pipeline operates independently from execute pipeline Fetch independently Program Bus E Data Read Buses (B,C,D) AM I PU IU AU DU F D Data Write Buses (E,F) IEE, Slide 28 Copyrigh C55x Execute Pipeline C55x Execute D AD AC1AC2 R D - decode opcode decode opcode AD - compute address AC1 - gen read address AC2 - memory wait R - read operands X - execute W - write to memory D AD AC1AC2 R XW D AD AC1AC2 R IBQ 64x8 XW D AD AC1AC2 R 1-6 bytes E Data Read Buses (B,C,D) AM I IU AU DU F D Data Write Buses (E,F) XW D AD AC1AC2 R XW D AD AC1AC2 R XW D AD AC1AC2 R XW Execute pipeline fetches instructions instructions FROM the IBQ, then executes them IU performs fetch/decode from IBQ AU generates operand addresses AU/DU execute instructions X: result to register W: result to memory IEE, Slide 29 XW Copyrigh Execute Pipeline Phases 1 of 2 D Read six bytes from the instruction buffer queue. Decode an instruction pair or a single instruction. Dispatch instructions to the appropriate CPU functional units. Read STx_55 bits associated with data address generation: ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC) AD Read/modify registers involved in data address generation. Read/modify Perform operations that use the A-unit ALU. Perform Decrement ARx for the conditional branch instruction Decrement Evaluate the condition of the XCC instruction AC1 Memory read operations, send addresses on the appropriate CPU Memory address buses. address IEE, Slide 30 Copyrigh Execute Pipeline Phases 2 of 2 Execute AC2 Allows one cycle for memories to respond to read requests. R Read data from memory, I/O space, and MMR-addressed registers. Read A-unit registers Read Evaluate the conditions of conditional instructions. X Read/modify registers that are not MMR-addressed. Read/modify individual register bits. Set conditions. Evaluate the condition of the RPTCC instruction. W Write data to MMR-addressed registers or to I/O space (peripheral Write registers). registers). Write data to memory. Write IEE, Slide 31 Copyrigh Program 00_0000 C5510 Unified Memory Map Data 00_0000 MMRs 00_00C0 DARAM (32KW) 00_0060 01_0000 00_8000 Internal SARAM (128KW) 05_0000 02_8000 External FF_FFF F D(32) D(32) A(24) A(24) IEE, Slide 32 Program and data share the same map 2 ways to view the map: Prog Data 23 0 23 10 0 1. Program - (Bytes) 7F_FFF F C55xx C55xx core core - 16M x 8-bit, linear 24-bit addresses - Used by fetch/decode logic Used 2. Data (Words) 2. - 8M x 16-bit, segmented into 64K pages, 23-bit address - Most code written by a user will access data Copyrigh Memory Access IEE, Slide 33 16M bytes of memory are addressable as 16M program space or data space When the CPU uses program space to read When program code from memory, it uses 24-bit program addresses to reference bytes. addresses When program accesses data space, it uses 23-bit When addresses to reference 16-bit words. addresses In both cases, the address buses carry 24-bit In values, but during a data-space access, the least significant bit on the address bus is forced to 0. significant Copyrigh Data Memory Data space is divided into 128 main data pages (0 Data through 127) of 64K addresses each. through An instruction that references a main data page An concatenates a 7-bit main data page value with a 16-bit offset. offset. On data page 0, the first 96 addres...
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This document was uploaded on 03/12/2014 for the course EEE 404 at Arizona State University.

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