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Unformatted text preview: it accumulator halves are sign extended if they
are shifted right.
During a signed shift of an accumulator, if it is a 32bit operation (M40 = 0), bit 31 is copied into the
accumulator’s guard bits (39–32).
Set and reset SXMD by: IEE, Slide 85 BCLR SXMD ; Clear SXMD
BSET SXMD ; Set SXMD Copyrigh XF Bit of ST1_55 The XF bit is a general-purpose output
bit that can be manipulated by software
and exported to XF pin of the DSP
To clear and set XF:
BCLR XF ; Clear XF BSET XF ; Set XF IEE, Slide 86 Copyrigh AR0LC–AR7LC Bits of ST2_55 AR0LC–AR7LC Bits are the
linear/circular configuration bits of the
eight auxiliary registers, AR0–AR7.
If ARnLC= 0 ARn is used for linear
addressing If ARnLC=1 ARn is used for circular
addressing To clear and set the ARnLC bits
BCLR AR0LC ; Clear AR0LC BSET AR0LC ; Set AR0LC IEE, Slide 87 Copyrigh ARMS Bit of ST2_55 ARMS AR mode switch bit determines the CPU mode
used for the AR indirect addressing mode:
used ARMS=0 « DSP mode operands », provides efficient
execution of DSP intensive applications. Among these
operands are those that use reverse carry propagation
when adding to or subtracting from a pointer.
Short-offset operands are not available.
Short-offset ARMS=1 « Control mode operands », enables
optimized code size for control system applications.
The short-offset operand *ARn(short(#k3)) is
available. IEE, Slide 88 BCLR ARMS ; Clear ARMS (happens at run time)
.ARMS_off ; Tell assembler ARMS = 0
BSET ARMS ; Set ARMS (happens at run time)
.ARMS_on ; Tell assembler ARMS = 1 Copyrigh CDPLC Bit of ST2_55 CDPLC is the CDP linear/circular
configuration bit. It determines whether
the coefficient data pointer (CDP) is
used for linear addressing or circular
CDPLC=0 Linear addressing CDPLC=1 Circular addressing To clear and set CDPLC : IEE, Slide 89 BCLR CDPLC ; Clear CDPLC
BSET CDPLC ; Set CDPLC Copyrigh DBGM Bit of ST2_55 IEE, Slide 90 DBGM: Debug mode bit gives the ability to
block debug events during time-critical
portions of a program:
If DBGM=0 Debug is enable
If DBGM=1 Debug is disable, emulator
cannot access memory or registers.
Software breakpoints still cause the CPU to
halt, but hardware breakpoints or halt
requests are ignored.
Before interrupt service routine CPU sets the
DBGM bit to disable.
Return-from-interrupt instruction restores
the DBGM bit from the data stack.
the Copyrigh EALLOW Bit of ST2_55
/RDM Bit of ST2_55 EALLOW is the Emulation access enable bit.
It enables or disables write access to non-CPU
emulation RDM, Rounding mode bit, defines the type of
rounding performed by the CPU:
rounding IEE, Slide 91 If EALLOW =0 Emulation access is disabled
If EALLOW=1 Emulation is enabled If RDM =0 the mode is Round to the infinite.
CPU adds 8000h (215) to the operand then clears
bits 15 through 0 to generate a rounded result in a
24- or 16-bit representation.
24- Copyrigh Round Mode RDM
If RDM=1 then Round to the nearest.
The rounding depends on bits 15 through 0 of
the operand, and bits 15–0 are cleared
•For compatibility with TMS320C54x code,
RDM must be 0 and C54CM = 1.
•To clear or set
BCLR RDM ; Clear RDM
BSET RDM ; Set RDM IEE, Slide 92 Copyrigh CACLR Bit of ST3_55 CACLR, Cache clear bit, enables to check
when the process for clearing the program
cache is complete:
cache If cache is cleared, the content of the prefetch
queue in the instruction buffer unit is
CACLR bit can be changed (pipeline protect): IEE, Slide 93 CACLR=0 Complete. The cache hardware clears
the CACLR bit when the process is complete.
CACLR=1 Not complete. All cache blocks are
invalid. The number of cycles needed to clear the
cache depends on the memory architecture.
cache BCLR CACLR ; Clear CACLR
BSET CACLR ; Set CACLR Copyrigh CAEN Bit of ST3_55 IEE, Slide 94 CAEN is the Cache enable bit that
enables or disables the program cache:
CAEN =0 then cache is disabled.
All program requests are handled either
by the internal memory or the external
memory, depending on the address
CAEN=1 Cache is enabled. Program
code is fetched from the cache, from the
internal memory, or from the external
memory, depending on the address
decoded. Copyrigh CAFRZ Bit of ST3_55 CAFRZ is « Cache freeze bit » that freezes
the program cache.
IF CAFRZ =0, the cache is in its default
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This document was uploaded on 03/12/2014 for the course EEE 404 at Arizona State University.
- Spring '14