The cache hardware clears caclr0 the caclr bit when

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Unformatted text preview: ing mode (updated) operating If CAFRZ=1, the cache is frozen (the cache If content is locked). content To change CAFRZ bit use: IEE, Slide 95 BCLR CAFRZ ; Clear CAFRZ BSET CAFRZ ; Set CAFRZ Copyrigh CBERR Bit of ST3_55 IEE, Slide 96 CBERR is the « CPU bus error flag » The CBERR bit is set when an internal bus error is The detected. An error causes the CPU to set the bus error interrupt flag (BERRINTF) in IFR1. The interrupt service routine for the bus error The interrupt (BERRINT) must clear the CBERR bit before it returns control to the interrupted program before using: BCLR CBERR ; Clear CBERR using: BCLR If CBERR =0 The flag has been cleared by program If or by a reset. or CBERR=1 An internal bus error has been detected. Copyrigh CLKOFF Bit of ST3_55 CLKOFF bit disables CLKOUT CLKOFF If CLKOFF = 1, the output of the If CLKOUT pin is disabled and remains at a high level. at Set and clear by: BCLR CLKOFF ; Clear CLKOFF BSET CLKOFF ; Set CLKOFF IEE, Slide 97 Copyrigh HINT Bit of ST3_55 IEE, Slide 98 HINT: Host interrupt bit is used to send HINT: an interrupt request to a host processor by the way of the host port interface. by To produce an active-low interrupt To pulse clear and then set the HINT bit: pulse BCLR HINT ; Clear HINT BSET HINT ; Set HINT Copyrigh MPNMC Bit of ST3_55 MPNMC • MPNMC defines the Microprocessor / MicroMPNMC computer mode computer • MPNMC reflects the logic level on the MP/MC pin when the pin is sampled at reset pin • The MPNMC bit enables or disables the on-chip ROM. ROM. If MPNMC=0 Microcomputer mode. The on-chip ROM is enabled; it is addressable in program space. ROM If MPNMC=1 Microprocessor mode. The on-chip ROM is disabled; it is not in the program-space map. ROM IEE, Slide 99 Copyrigh SATA Bit of ST3_55 SATA is the Saturation mode bit for the A SATA unit unit SATA bit determines whether the CPU SATA saturates overflow results of the A-unit arithmetic logic unit (A-unit ALU): arithmetic If SATA=0 No saturation is performed. If SATA=1 On. If result is in overflow, If result is saturated to 7FFFh or 8000h (for positive or negative overflow respectively). positive Can be cleared and set by: IEE, Slide 100 BCLR SATA ; Clear SATA BSET SATA ; Set SATA Copyrigh SMUL Bit of ST3_55 SMUL is the Saturation-on-multiplication SMUL mode bit: mode If SMUL =0 Off If SMUL =1 On. If SMUL=1 forces the product of the two SMUL=1 negative numbers to be a positive number. negative For multiply-and-accumulate/subtract For instructions, the saturation is performed after the multiplication and before the addition/subtraction. addition/subtraction. Clear and set SMUL with : IEE, Slide 101 BCLR SMUL ; Clear SMUL BSET SMUL ; Set SMUL Copyrigh SST Bit of ST3_55 IEE, Slide 102 SST is the Saturate-on-store mode bit used SST in the C54-compatible mode (C54CM=1) in If C54CM=0 SST is ignored by the C55x. If If C54CM = 1: SST turns the saturationon-store mode on or off. SST= 0 no saturation SST=1 CPU saturates a shifted or SST=1 unshifted accumulator value before storing it. The saturation depends on the value of the sign-extension mode bit (SXMD) (SXMD) Copyrigh...
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