These vectors can be mapped to memory shared by the

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Unformatted text preview: ndicates that the interrupt is pending, or This waiting for acknowledgement from the CPU. waiting One can read IFRs to identify pending interrupts, and write to the IFRs to clear pending interrupts. and To clear an interrupt request write a 1 to the To corresponding IFR bit. All pending interrupts can be cleared by writing All the current contents of the IFR back into the IFR. the Acknowledgement of a hardware interrupt request also clears the corresponding IFR bit. request A device reset clears all IFR bits. device Copyrigh RTOSINTF Bit in IFR1 RTOSINTF bit 10 in IFR1 is an interrupt flag RTOSINTF bit for the real-time operating system interrupt, RTOSINT interrupt, When you read the RTOSINTF bit, When If RTOSINTF=0, RTOSINT is not pending. If RTOSINTF If RTOSINTF=1, RTOSINT is pending. If RTOSINTF IEE, Slide 61 To clear this flag bit to 0 (and clear its To corresponding interrupt request), write a 1 to the bit. to Copyrigh DLOGINTF and BERRINTF Bits in IFR1 IEE, Slide 62 DLOGINTF is the bit 9 of IFR1 for the datalog interrupt, DLOGINTF If DLOGINTF bit is: 0 then DLOGINT is not pending. 1 then DLOGINT is pending. BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the BERRINTF bus error interrupt, BERRINT bus If BERRINTF bit is: 0 then BERRINT is not pending. 1 then BERRINT is pending. To clear these flags to 0 (and clear the corresponding To interrupt request), write a 1 to the bit. interrupt Copyrigh IF16–IF23 Bits in IFR1 /IF2–IF15 Bits in IFR0 These are flag bits in IFR1 or IFR0 If Interrupt flag IFx is: IEE, Slide 63 0 then the interrupt associated with then interrupt vector x is not pending. interrupt 1 then the interrupt associated with then interrupt vector x is pending. interrupt To clear a flag bit to 0 (and clear its To corresponding interrupt request), write a 1 to the bit. to Copyrigh Interrupt Enable Registers (IER0, IER1) IEE, Slide 64 To enable a maskable interrupt, set its To corresponding bit in IER0 or IER1 to 1. corresponding To disable a maskable interrupt, clear To its corresponding enable bit to 0. At reset, all the IER bits are cleared to At 0, disabling all the maskable interrupts. 0, IER1 and IER0 are not affected by a IER1 software reset instruction or by a DSP hardware reset. hardware Initialize these registers before you globally enable (INTM = 0) the maskable interrupts. maskable Copyrigh RTOSINTE, DLOGINTE, BERRINTE and RTOSINTE, IE16–IE23 Bits in IER1 & IE2–IE15 Bits in IER0 RTOSINTE is the Enable bit for the RTOSINTE real-time operating system interrupt,RTOSINT interrupt,RTOSINT DLOGINTE is the Enable bit for the DLOGINTE data log interrupt, DLOGINT data BERRINTE is the Enable bit for the bus BERRINTE error interrupt, BERRINT error IE16–IE23 bits are enable flags IE16–IE23 interrupt associated with interrupt vector x. vector IE2–IE15 bits are enable flags interrupt IE2–IE15 associated with interrupt vector x. associated IEE, Slide 65 Copyrigh Debug Interrupt Enable Registers Debug (DBIER0, DBIER1) (DBIER0, IEE, Slide 66 DBIER1 and DBIER0 are used only when the DBIER1 CPU is halted in the real-time emulation mode of the debugger. mode A maskable interrupt enabled in a DBIER is maskable defined as a time-critical interrupt. defined When the CPU is halted in the real-time When mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an interrupt enable register (IER1 or IER0). or Write the DBIERs to enable or disable timecritical interrupts. To enable an interrupt, set critical its corresponding bit. its Copyrigh Registers for Controlling Repeat Loops IEE, Slide 67 Single-Repeat Registers (RPTC, CSR) Block-Repeat Registers (BRC0–1, Block-Repeat BRS1, RSA0–1, REA0–1) BRS1, These CPU registers are mapped in These memory memory Copyrigh Status Registers (ST0_55–ST3_55) The four 16-bit registers (ST0_55, ST1_55, ST2_55 The and ST3_55) contain control bits and flag bits and Control bits affect the operation of the C55x DSP Control Flag bits reflect the current status of the DSP or Flag indicate the results of operations. indicate ST0_55, ST1_55, and ST3_55 are each accessible at ST0_55, two addresses two IEE, Slide 68 At one address, all the TMS320C55x bits are available. At the other address (the protected address), some of the bits At cannot be modified. cannot The protected address is provided to support TMS320C54x The code that was written to access ST0, ST1, and PMST (the C54x counterpart of ST3_55). C54x Copyrigh Contents of Status Registers IEE, Slide 69 Copyrigh ST0_55 Contents ACOV0, ACOV1, ACOV2, and ACOV3 bits ACOV0, give for each of the four accumulators its own overflow flag CARRY: this bit is the Carry/borrow CARRY: detection and...
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This document was uploaded on 03/12/2014 for the course EEE 404 at Arizona State University.

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