Auxiliary copyrigh data page register xdp dp iee

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Unformatted text preview: ressing mode, DPH is concatenated with a 16-bit immediate value to form a 23-bit address. form Copyrigh DP/ XDP Accesses IEE, Slide 52 XDP Extended data page register Accessible XDP via dedicated instruction only. XDP is not a register mapped to memory. register DP Data page register accessible via dedicated DP instructions and as a memory-mapped register register DPH High part of extended data page DPH Register is accessible via dedicated instructions and as a memory-mapped register register Copyrigh Peripheral Data Page Register (PDP) Peripheral IEE, Slide 53 The 9-bit peripheral data page register The (PDP) selects a 128-word page within the 64K-word I/O space. 64K-word Copyrigh Stack Pointers (XSP / SP, XSSP / SSP) IEE, Slide 54 The data stack pointer (SP), a system stack ), pointer (SSP), and an associated extension pointer ), register (SPH) are the CPU stack registers register When accessing the data stack, the CPU concatenates SPH with SP to form an extended SP that is called XSP. extended XSP contains the address of the value last XSP pushed onto the data stack. pushed SPH holds the 7-bit main data page of memory, and SP points to the specific word on that page. that Copyrigh Stack Register Accesses IEE, Slide 55 XSP Extended data stack pointer is accessible XSP via dedicated instructions only. XSP is not a register mapped to memory. register SP Data stack pointer is accessible via SP dedicated instructions and as a memorydedicated mapped register XSSP Extended system stack pointer is XSSP accessible via dedicated instructions only. XSSP is not a register mapped to memory. XSSP SSP System stack pointer is accessible via SSP dedicated instructions and as a memorydedicated mapped register SPH High part of XSP and XSSP is accessible SPH via dedicated instructions and as a memoryvia mapped register. mapped Copyrigh Program Flow Registers (PC, RETA, CFCT) IEE, Slide 56 PC Program counter is a 24-bit register holds PC the address of the 1 to 6 bytes of code being decoded in the I unit. decoded When the CPU performs an interrupt or call, When the current PC value (the return address) is stored on the stack, and then PC is loaded with a new address. with When the CPU returns from an interrupt When service routine or a called subroutine, the return address is restored to PC. Copyrigh RETA Return Address Register CFCT Control-flow Context Register If the selected stack configuration uses the If fast-return process fast-return IEE, Slide 57 RETA is a temporary holding place for the return RETA address and CFCT is a temporary holding place for the 8-bit loop context while a subroutine is being executed executed CFCT, along with RETA, enables the efficient CFCT, execution of multiple layers of subroutines execution You can read from or write to RETA and CFCT as You a pair with dedicated, 32-bit load and store instructions. instructions. The Loop context is stored into CFCT, when an The interrupt or a subroutine call occur the loop context is stored in CFCT and restored on return. Copyrigh Registers For Managing Interrupts IEE, Slide 58 IVPD Point to the DSP interrupt vectors (IV0–IV15 and IV24–IV31) (IV0–IV15 IVPH Point to the host interrupt vectors IVPH (IV16–IV23) (IV16–IV23) IFR0, IFR1 Indicate which maskable IFR0, interrupts have been requested interrupts IER0, IER1 Enable or disable maskable IER0, interrupts DBIER0, DBIER1 Configure select maskable DBIER0, interrupts as time-critical interrupts interrupts Copyrigh Interrupt Vector Pointers (IVPD, IVPH) Two 16-bit interrupt vector pointers (IVPD and IVPH) point to interrupt vectors in program space. point IEE, Slide 59 The DSP interrupt vector pointer (IVPD) points to the The 256-byte program page that contains the DSP interrupt vectors (IV0–IV15 and IV24–IV31). These vectors can be mapped to memory that is allocated to the DSP only. the The host interrupt vector pointer (IVPH) points to the The 256-byte program page that contains the host interrupt vectors (IV16–IV23). These vectors can be mapped to memory shared by the DSP and the host processor, so that the host processor can define the associated interrupt service routines. interrupt If IVPD and IVPH have the same value, all of the If interrupt vectors will be in the same 256-byte program page. Copyrigh Interrupt Flag Registers (IFR0, IFR1) The 16-bit interrupt flag registers, IFR1 and The IFR0, contain flag bits for all the maskable interrupts: interrupts: IEE, Slide 60 When a maskable interrupt request reaches the When CPU, the corresponding flag is set to 1 in one of the IFRs. This i...
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