Bits each of portion can be accessed individually by

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Unformatted text preview: -bit extremum selections update When TRN0 and TRN1 based on the comparison of two accumulators’ high words and low words. accumulators’ TRN0 is updated based on the comparison of the TRN0 accumulators high words; accumulators TRN1 is updated based on the comparison of the low words. When performing a single 40-bit extremum selection the When selected transition register (TRN0 or TRN1) is updated based on the comparison of two accumulators throughout their 40 bits. their TRN0 and TRN1 can hold transition decisions for the TRN0 path to new metrics in Viterbi algorithm implementations. implementations. Copyrigh Temporary Registers (T0–T3) Four 16-bit general-purpose temporary Four registers: T0–T3 can be used for: registers: IEE, Slide 44 Hold one of the memory multiplicands for Hold multiply, multiply-and-accumulate, and multiplymultiply, and-subtract instructions Hold the shift count used in addition, subtraction, and load instructions performed in the D unit and Keep track of more pointer values by swapping the contents of the auxiliary registers (AR0–AR7) and the temporary registers (using a swap instruction) instruction) Hold the transition metric of a Viterbi butterfly for dual 16-bit operations performed in the D-unit ALU ALU Copyrigh Registers Used to Address Data Space and Registers I/O Space I/O Auxiliary Registers (XAR0–XAR7 / AR0–AR7) The CPU includes eight extended auxiliary The registers XAR0–XAR7 registers Each high part ( ARnH) is used to specify the 7bit main data page for accesses to data space. Each low part ( ARn) can be used as: IEE, Slide 45 A 16-bit offset to the 7-bit main data page (to form a 23-bit 16-bit address) address) A bit address (in instructions that access individual bits or bit pairs) pairs) A general-purpose register or counter general-purpose Copyrigh ARn and XARn Access ARn Auxiliary register n and XARn Extended ARn auxiliary register n are accessible via dedicated instructions . ARn is mapped to memory ARn XARn is not mapped to memory. ARnH high part of extended auxiliary register ARnH n is Not individually accessible. To access ARnH, you must access XARn. To IEE, Slide 46 XAR0–XAR7 or AR0–AR7 are used in the XAR0–XAR7 AR indirect addressing mode and the dual AR indirect addressing mode. Basic arithmetical, logical and shift operations Basic can be performed on AR0–AR7 in the A-unit arithmetic logic unit (ALU). arithmetic Copyrigh Coefficient Data Pointer (XCDP / CDP) IEE, Slide 47 CDP is a coefficient data pointer, and CDPH CDP an associated extension register, concatenate the two form the extended CDP that is called XCDP CDPH is used to specify the 7-bit main data CDPH page for accesses to data space. page The low 16 bits part (CDP) can be used as: A 16-bit offset to the 7-bit main data page (to form a 23-bit address) (to A bit address (in instructions that access individual bits or bit pairs) individual A general-purpose register or counter general-purpose Copyrigh XCDP and CDP Accesses IEE, Slide 48 XCDP Extended coefficient data pointer is XCDP accessible via dedicated instructions only. accessible XCDP is not a register mapped to memory. CDP Coefficient data pointer is accessible via CDP dedicated instructions and as a memorydedicated mapped register CDPH High part of extended coefficient data CDPH pointer is accessible via dedicated instructions and as a memory-mapped register and Copyrigh Circular Buffer Start Address Registers Circular (BSA01, BSA23, BSA45, BSA67, BSAC) IEE, Slide 49 The CPU includes five 16-bit circular buffer The start address registers start Each buffer start address register is Each associated with a particular pointer A buffer start address is added to the pointer buffer only when the pointer is configured for circular addressing in status register ST2_55. circular Copyrigh Circular Buffer Size Registers (BK03, BK47, BKC) IEE, Slide 50 Three 16-bit circular buffer size registers Three specify the number of words (up to 65535) in a circular buffer. Each buffer size register is associated with Each particular pointers particular In the TMS320C54x-compatible mode In (C54CM = 1), BK03 is used for all the auxiliary registers, and BK47 is not used. auxiliary Copyrigh Data Page Register (XDP / DP) IEE, Slide 51 Data page register, DP, and associated Data extension register DPH can be concatenated to form an extended DP that is called XDP to The high part (DPH) is used to specify the 7bit main data page for accesses to data space. The low part specifies a 16-bit offset (local The data page) that is concatenated with the main data page to form a 23-bit address. data In the DP direct addressing mode, XDP In specifies a 23-bit address, and in the k16 absolute add...
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