Indicate st055 st155 and st355 are each accessible at

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Unformatted text preview: depends on the M40 bit in ST1_55: ST1_55: IEE, Slide 70 M40 = 0: Carry/borrow is detected with respect to M40 bit position 31. bit M40 = 1: Carry/borrow is detected with respect to bit position 39. bit For compatibility with TMS320C54x code, For make sure M40 = 0. make Copyrigh DP Status Bits in ST0_55 DP is a copy in ST0_55 of the 9 most DP significant bits of the data page register (DP) significant This 9-bit field is provided for compatibility This with the TMS320C54x DSPs. with TMS320C55x DSPs have a data page pointer independent of ST0_55. IEE, Slide 71 Any change to bits 15–7 of the data page register DP(15–7) is reflected in the DP status bits. DP(15–7) Any change to the DP status bits is reflected in Any DP(15–7). Copyrigh TC1 and TC2 Bits of ST0_55 TC1 and TC2 are Test/Control flag TC1 The main function of a test/control bits is to hold the The result of a test performed by specific instructions. result All the instructions that affect a test/control flag allow All you to choose whether TC1 or TC2 is affected. you TCx (where x = 1 or 2) or a Boolean expression of TCx TCx can be used as a trigger in any conditional instruction. instruction. You can clear and set TC1 and TC2 with the You following instructions: following o o o o IEE, Slide 72 BCLR TC1 ; Clear TC1 BSET TC1 ; Set TC1 BCLR TC2 ; Clear TC2 BSET TC2 ; Set TC2 Copyrigh ASM Bit Field of ST1_55 IEE, Slide 73 ASM is the Accumulator shift mode bit In the TMS320C54x-compatible mode , In ASM supplies a shift value in the range –16 through 15 (5 bits in 2’s complement). through If C54CM=1: C54x code running on the If C55x DSP, and ASM contains the shift count for instructions that specify a shift of an accumulator value. an If C54CM = 0: ASM is ignored and the If shift count for an accumulator shift operation comes from the temporary register (T0, T1, T2, or T3) specified in the C55x instruction or from a constant embedded in the C55x instruction. embedded Copyrigh BRAF Bit of ST1_55 BRAF: Block-repeat active flag is used in the BRAF: TMS320C54x-compatible mode (C54CM = 1). TMS320C54x-compatible BRAF indicates/controls the status of a block-repeat operation. operation. If C54CM = 1 (C54x mode): BRAF is saved and If restored with ST1_55 during context switches caused by calls, interrupts, and returns. BRAF is automatically cleared when a far branch (FB) or far call (FCALL) instruction is executed. (FB) If C54CM = 0: BRAF is not used. The status of repeat If BRAF operations is maintained automatically by the CPU (see CFCT ) (see To stop or set an active block-repeat operation in the To C54x-compatible mode, you can use the following instruction: instruction: IEE, Slide 74 BCLR BRAF ; Clear BRAF BSET BRAF ; Set BRAF Copyrigh C16 Bit of ST1_55 C16 is the Dual 16-bit arithmetic mode bit used in the C16 C54x-compatible mode (C54CM = 1), execution of some instructions is affected by C16. some The arithmetic performed in the D-unit ALU depends The on C16: on If C16 =0 then for an instruction that is affected by C16, the D-unit If ALU performs one 32-bit operation (double-precision arithmetic) . ALU If C16=1 then an instruction that is affected by C16, the D-unit If ALU performs two 16-bit operations in parallel (dual 16-bit arithmetic). arithmetic). If C54CM = 0: The CPU ignores C16. The instruction If alone determines whether dual 16-bit arithmetic or 32-bit arithmetic is used. 32-bit You can clear and set C16 with the following instructions: IEE, Slide 75 BCLR C16 ; Clear C16 BSET C16 ; Set C16 Copyrigh C54CM Bit of ST1_55 C54CM is the TMS320C54x-compatible mode bit The C54CM bit determines whether the CPU will The support code that was developed for a TMS320C54x DSP: DSP: If C54CM=0 then the CPU supports code written for If a TMS320C55x (C55x) DSP. TMS320C55x If C54CM=1 then you can use code that was If originally developed for a TMS320C54x (C54x) DSP. originally In C54 mode all the C55x CPU resources remain available; the additional features on the C55x can be used for code optimization. used Change modes with the following instructions and Change assembler directives: assembler IEE, Slide 76 BCLR C54CM ; Clear C54CM (happens at run time) BSET C54CM ; Set C54CM (happens at run time) Copyrigh CPL Bit of ST1_55 IEE, Slide 77 CPL is the Compiler mode bit and determines CPL which of two direct addressing modes is active: which CPL=0 then Direct accesses to data space are CPL=0 made relative to the data page register (DP). made CPL=1 then Direct accesses to data space are CPL=1 made relative to the data stack pointer (SP). The DSP is said to be in compiler...
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This document was uploaded on 03/12/2014 for the course EEE 404 at Arizona State University.

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