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DSP
Change modes with the following instructions
Change
and assembler directives:
and BCLR CPL ; Clear CPL (happens at run
BCLR
time)
time) BSET CPL ; Set CPL (happens at run time) Copyrigh FRCT Bit of ST1_55 FRCT is the Fractional mode bit that
FRCT
sets the fractional mode on or off:
sets
FRCT=0 then results of multiply
FRCT=0
operations are not shifted.
operations
FRCT=1 then results of multiply
FRCT=1
operations are shifted left by 1 bit for
decimal point adjustment. You can clear and set FRCT with : IEE, Slide 78 This is required when you multiply two
This
signedQ15 values and you need a Q31
result.
result. BCLR FRCT ; Clear FRCT
BSET FRCT ; Set FRCT Copyrigh HM Bit of ST1_55 HM is the Hold mode bit used when the DSP
HM
acknowledges an active HOLD signal. It
places its external interface in the highplaces
impedance state.
impedance
Depending on HM, the DSP may also stop
Depending
internal program execution:
internal
HM=0 then the DSP continues executing
HM=0
instructions from internal program memory.
instructions
HM=1 then the DSP stops executing
HM=1
instructions from internal program memory.
instructions
To clear and set HM: IEE, Slide 79 BCLR HM ; Clear HM
BSET HM ; Set HM Copyrigh INTM Bit of ST1_55 IEE, Slide 80 INTM is the Interrupt mode bit, it globally enables
or disables the maskable interrupts. If INTM =0 All unmasked interrupts are enabled. If INTM=1 All maskable interrupts are disabled.
Software interrupt instruction and software reset
Software
instruction, set INTM before branching to the
interrupt service routine.
interrupt
Before executing an interrupt service routine (ISR),
Before
the CPU automatically sets the INTM bit to globally
disable the maskable interrupts. The ISR can redisable
enable the maskable interrupts by clearing the INTM
enable
bit.
bit. BCLR INTM ; Clear INTM BSET INTM ; Set INTM
A returnfrominterrupt instruction restores the
INTM bit from the data stack.
INTM Copyrigh M40 Bit of ST1_55 M40 is the computation mode bit for the D unit M40 bit selects one of two computation modes for the
M40
D unit:
unit:
If M40=0 then the sign bit is extracted from bit
If
position 31:
position IEE, Slide 81 During arithmetic, the carry is determined with respect to
bit position 31.
bit
Overflows are detected at bit position 31.
Overflows
During saturation, the saturation value is 00 7FFF FFFFh
(positive overflow) or FF 8000 0000h (negative overflow).
(positive
Accumulator comparisons versus 0 are done using bits 31–0.
Accumulator
Shift or rotate operations are performed on 32bit values.
Shift Copyrigh M40 Bit Note: In the TMS320C54x compatible
Note:
mode (C54CM = 1), CM=0
mode M= 40bit mode. In this mode the sign bit is
M=
extracted from bit position 39, the same as
before on 40 bits.
before
To clear and set M40 : IEE, Slide 82 An accumulator’s sign bit is extracted from bit
An
position 39.
position
Accumulator comparisons versus 0 are done
using bits 39–0.
using
Signed shifts are performed as if M40 = 1. BCLR M40 ; Clear M40
BSET M40 ; Set M40 Copyrigh SATD Bit of ST1_55 SATD is the Saturation mode bit, it determines
SATD
whether the CPU saturates overflow results in the D
unit:
unit:
SATD =0 No saturation is performed.
SATD=1 If an operation result gives an overflow, the
SATD=1
result is saturated. The saturation depends on the
value of the M40 bit:
value To clear and set SATD : IEE, Slide 83 M40 = 0 The CPU saturates the result to 00 7FFF FFFFh
M40
(positive overflow) or FF 8000 0000h (negative overflow).
(positive
M40 = 1 The CPU saturates the result to 7F FFFF FFFFh
M40
(positive overflow) or 80 0000 0000h (negative overflow).
(positive
BCLR SATD ; Clear SATD
BSET SATD ; Set SATD Copyrigh SXMD Bit of ST1_55 IEE, Slide 84 SXMD is the Signextension mode bit. It sets
SXMD
and resets the signextension mode, which
affects accumulator operations that are
performed in the D unit:
performed
If SXMD=0 then signextension mode is off:
For 40bit operations, 16bit or smaller
For
operands are zero extended to 40 bits.
operands
For the conditional subtract instruction, any
For
16bit divisor produces the expected result.
16bit
When the Dunit arithmetic logic unit (ALU)
When
is locally configured in its dual 16bit mode,
16bit values used in the higher part of the D16bit
unit ALU are zero extended to 24 bits. Copyrigh SXMD
SXMD If SXMD=1 then 40bit operations, 16bit or smaller
operands are sign extended to 40 bits.
When the Dunit ALU is locally configured in its dual
16bit mode, 16bit values used in the higher part of
the Dunit ALU are sign extended to 24 bits.
16b...
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This document was uploaded on 03/12/2014 for the course EEE 404 at Arizona State University.
 Spring '14

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