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Unformatted text preview: ses (00 0000h00 005Fh) are reserved for the memory-mapped
registers IEE, Slide 34 Copyrigh I/O Memory I/O space is separate from data/program space and is
available only for accessing registers of the
peripherals on the DSP. The word addresses in I/O
space are 16 bits wide, enabling access to 64K
locations The CPU uses the data-read address bus DAB for
reads and data-write address bus EAB for writes.
When the CPU reads from or writes to I/O space, the
16-bit address is concatenated with leading 0s.
Example, suppose an instruction reads a word at the 16-bit address
0102h. DAB carries the 24-bit value 00 0102h.
0102h. IEE, Slide 35 Copyrigh C5510 Peripheral Overview
Memory EHPI C5510 DMA
CPU Boot MCBSP
- 16-bit host access to memory 3 Multi-Channel Buffered SPs
- High speed sync serial comm
- 6 Channels (rotating priority) General Purpose I/O
- 8-bit i/o port EMIF
- Access to EPROM, SRAM, SBSRAM,
- Two 20-bit timer/counters BOOT Loader
- From external memory, Host, McBSP
IEE, Slide 36 Power-Down Modes
Instruction Cache (24K bytes) Copyrigh CPU Registers Description
C54x and C55x Copyrigh CPU Registers C54x vs C55x IEE, Slide 38 The study of CPU registers gives a very
good understanding on the processor
The C54x DSP is code compatible with
the C55x, therefore registers have the
same functionally in both DSPs.
Registers in the C55x are more complex
so we will see their role and give
equivalents for the C54x.
The following table summarizes the
differences. Copyrigh C55x CPU Registers and
C54x Equivalents 1 of 3
Abbreviation Name Size C54x AC0–AC3 Accumulators 0 through 3 40 bits A,B AR0–AR7 Auxiliary registers 0 to 7 16 bits same BK03, BK47, BKC Circular buffer size registers 16 bits BK BRC0, BRC1 Block-repeat counters 0 & 1 16 bits BRC BRS1 BRC1 Save register 16 bits none BSA01,
BSA67, BSA Circular buffer start address
registers 16 bits none CDP Coefficient data pointer (low
part of XCDP) 16 bits none CDPH High part of XCDP 7 bits none IEE, Slide 39 Copyrigh C55x CPU Registers and
C54x Equivalents 2 of 3
CFCT Control-flow context register 8 bits none CSR Computed single-repeat
register 16 bits none DBIER0,
DBIER1 Debug interrupt enable
registers 0 and 1 16 bits none DP Data page register (low
part of XDP) 16 bits DP(9 ) DPH High part of XDP 7 bits none IER0, IER1 Interrupt enable registers 0& 1 16 bits IMR IFR0, IFR1 Interrupt flag registers 0 and 1 16 bits IFR IVPD, IVPH Interrupt vector pointers 16 bits IPTR(9 ) PC Program counter 24 bits PC(16) PDP8 Peripheral data page register 9 bits none REA0, REA1 Block-repeat end address
registers 0 and 1 24 bits REA IEE, Slide 40 Copyrigh C55x CPU Registers and
C54 Equivalents 3 of 3
RETA Return address register 24 bits na. RPTC Single-repeat counter 16 bits na. RSA0, RSA1 Block-repeat start address registers 0
and 1 24 bits RSA SP Data stack pointer 16 bits SP SPH High part of XSP and XSSP 7 bits na. SSP System stack pointer 16 bits na. ST0_55–ST3_55 Status registers 0 through 3 16 bits ST0,ST1,
PMST T0–T3 Temporary registers 0 to 3 16 bits T TRN0, TRN1 Transition registers 0 and 1 16 bits TRN XAR0–XAR7 Extended auxiliary registers 0 through
7 23 bits na. XCDP Extended coefficient data pointer 23 bits na. XDP Extended data page register 23 bits na. XSP Extended data stack pointer 23 bits na. XSSP Extended system stack pointer 23 bits na. 7 bits C548, C549,
C5420 XPC(not C55)
IEE, Slide 41 Extended program counter Copyrigh Accumulators (AC0–AC3) The C55 contains four 40-bit accumulators:
AC0, AC1, AC2, and AC3 (The primary function of these
registers is to assist in data computation in the D unit: ALU,
MACs and the shifter. The four accumulators are equivalent:
any instruction that uses an accumulator can be
to use any one of the four.
to Each accumulator is partitioned into:
a low word (ACxL), a high word (ACxH), and eight guard
bits Each of portion can be accessed individually:
by using addressing modes that access the memory-mapped
registers. IEE, Slide 42 In the TMS320C54x-compatible mode (C54CM = 1),
accumulators AC0 and AC1 correspond to
TMS320C54x accumulators A and B, respectively.
TMS320C54x Copyrigh Transition Registers (TRN0, TRN1) The two transition registers are used in the compareand-select-extremum instructions: IEE, Slide 43 When performing two 16...
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- Spring '14