Topic 08 Prb Solns

Topic 08 Prb Solns - 7.21. What are the rise time, fafl...

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Unformatted text preview: 7.21. What are the rise time, fafl time, and average prop— agation delay for a symmetrical CMOS inverter with (W/L)N =2/1, (W/LLD = 5/1, VDD =5 V, and C = 0.25 pF? 7.21 ' V ‘1’ 2V V 5—1 W 2 T =RmC 4 H m —1 + “V =R C 1114—— —1+_ =1.29 1.29(0.25x10-”) ——-—"—"'—_2 2 T(25x10**")(5 —1) T +17 Truffle: 1-611” 1 TPLH=TPHL ‘ TP =M=L61m 1:} = If =2’EPHL =3.22 us This W MT (P112) ML W Lee 58mm 7‘3 “if 15:. \rw/FWW Ft: M meg, fem-W 7.22. What are the rise time, fall time, and average prop- agation delay for a minimum size CMOS inverter in which both W/ L ratios are 2/1? Assume a load capacitance of 0.5 13F and VDD = 5 V. _ f _ 1 -. flame 4 M _1 +flL : RWCW 9—1 -1J+_2_ =129Rmc VH+VL VH—VZN 5+0 5—1 1.29£0.5x10'122 1.29(0.5x10"”2 : 3.23 ns I “(PM =1.29RMPC = ' = 8.06 ns %(25x10‘6X5—1) I ‘ %(10x10"6X5-1) TPHL = rpzfl'igfiffififis ns | rf=2rm=a46 ns I rr=2TPLH=16Jns Sea Gamma/s ch/[A to (77,04? ...
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This homework help was uploaded on 04/07/2008 for the course EE 307 taught by Professor Braun during the Winter '08 term at Cal Poly.

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Topic 08 Prb Solns - 7.21. What are the rise time, fafl...

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