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Unformatted text preview: ution with an AND gate at the output might have fewer
gates or gate inputs. A two-level OR-AND circuit corresponds
to a product-of-sums expression for the function. This can be
obtained from the 0′s on the Karnaugh map as follows: f ′ = c′d + ab′c′ + cd + a′b′c (7-3)
f = (c + d)(a′ + b + c)(c′ + d′)(a + b + c′) (7-4)
Equation (7-4) leads directly to a two-level OR-AND circuit. Figure 7-5 To get a three-level circuit with an AND gate output, we
partially multiply out Equation (7-4) using (X + Y)(X + Z) = X +
f = [c + d(a′ + b)][c′ + d′(a + b)] (7-5)
Equation (7-5) would require four levels of gates to realize;
however, if we multiply out d′(a + b) and d(a′ + b), we get f = (c + a′d + bd)(c′ + ad′ + bd′) (7-6)
which leads directly to a three-level AND-OR-AND circuit. Section 7.1 (p. 194)
Figure 7-6 This example: best two-level solution had an AND gate at
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.
- Spring '08