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Unformatted text preview: based on
DeMorgan′s
Laws Figure 714: Alternative Gate Symbols Figure 716: Conversion to
NOR Gates Figure 715:
NAND Gate Circuit
Conversion Design of TwoLevel, MultipleOutput
Circuits Solution of digital design problems often requires the realization
of several functions of the same variables. Although each
function could be realized separately, the use of some gates in
common between two or more functions sometimes leads to a
more economical realization.
Example:
Figure 717:
Conversion of ANDOR
Circuit to NAND Gates Design a circuit with four inputs and three outputs which realizes
the functions F1(A, B, C, D) = Ʃ m(11, 12, 13, 14, 15)
F2(A, B, C, D) = Ʃ m(3, 7, 11, 12, 13, 15)
F3(A, B, C, D) = Ʃ m(3, 7, 12, 13, 14, 15) (722)
Section 7.6 (p. 204) Realization of functions
separately (9 Gates) F1(A, B, C, D) = Ʃ m(11, 12, 13, 14, 15)
F2(A, B, C, D) = Ʃ m(3, 7, 11, 12, 13, 15)
F3(A, B, C, D) = Ʃ m(3, 7, 12, 13, 14, 15) Figure 719:
Realization of Equations
(722) Another example of sharing gates among multiple
outputs to reduce cost.
f1 = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
f2 = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15)
f3 = Ʃ m(6, 7, 8, 9, 13, 14, 15) Realization of functions
with shared gates (lower
overall cost) (7 Gates) Figure 721 MultipleOutput Realization of Eqns (722)
Minimal Solution
In this example,
the best solution
is obtained by
not combining
the circled 1 with
adjacent 1’s. f1 = a′bd + abd +
ab′c′ + b′c f2 = c + a′bd f3 = bc + ab′c′ +
abd Figure 722 The procedure
for design of
singleoutput,
multilevel
NAND and
NORgate
circuits also
applies to
multipleoutput
circuits The solution with the
maximum number of
common terms is not
necessarily the best
solution, as illustrated
by this example. Figure 723...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.
 Spring '08
 Brown
 Gate

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