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Unformatted text preview: t three-level solution had an OR gate at output.
General: for minimum, must find both circuit with AND-gate
output and with OR-gate output. Figure 7-7 Figure 7-5 Figure 7-6 NAND gates NOR gates Figure 7-8(a) shows a three-input NAND gate. The small circle (or
“bubble”) at the gate output indicates inversion, so the NAND gate
is equivalent to an AND gate followed by an inverter, as shown in
Figure 7-8(b). The gate output is Figure 7-9(a) shows a three-input NOR gate. The small circle at the
gate output indicates inversion, so the NOR gate is equivalent to an
OR gate followed by an inverter. The gate output is F = (A + B + C)′ = A′B′C′ F = (ABC)′ = A′ + B′ + C′ Figure 7-8: NAND Gates Figure 7-9: NOR Gates Functionally Complete Set of Gates AND and NOT are a functionally complete set of gates
because OR can also be realized using AND and NOT: Section 7.2 (p. 196) NAND Gates
Similarly, any function can be realized using only
NAND gates: Figure 7-10: NAND Gate Realization of NOT,
AND, and OR Design of Two-Level NAND-Gate Circuits
A two-level circuit composed of AND and OR gates is easily
converted to a circuit composed of NAND gates or NORE gates
using F = (F′)′ and then applying DeMorgan′s laws: Design of Two-Level NAND-Gate Circuits
The following example illustrates conversion of a minimum sum-ofproducts for...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.
- Spring '08