Chapter 07 - Multilevel Logic-2x2(1)

Simplify the switching function to be realized 2

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 + P 2 + • • • F = (l1′l2′ • • • P1′P2′ • • •)′ Figure 7-12: AND-OR to NAND-NAND Transformation Figure 7-12: AND-OR to NAND-NAND Transformation Design of Multi-Level NAND- and NOR-Gate Circuits The following procedure may be used to design multi-level NAND-gate circuits: 1. Simplify the switching function to be realized. 2. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND gate outputs cannot be used as ANDgate inputs; OR-gate outputs cannot be used as OR-gate inputs. 3. Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged, leave the inputs to levels 2,4,6,… unchanged. Invert any literals which appear as inputs to levels 1,3,5,… Section 7.4 (p. 200) Figure 7-13: Multi-Level Circuit Conversion to NAND Gates Alternative Gate Symbols Logic designers who design complex digital systems often find it convenient to use more than one representation for a given type of gate. For example, an inverter can be represented by Section 7.5 (p. 201) Equivalent gate symbols...
View Full Document

This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas.

Ask a homework question - tutors are online