Chapter 10 - VHDL Introduction-2x2(1)

5 p 298 figure 9 17 an 8 word x 4 bit rom 1 library

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Unformatted text preview: 0101010101010101”; constant ONE_WORD: SHORT_WORD := (others => ‘1’); Section 10.5 (p. 298) Figure 9-17: An 8-Word x 4-Bit ROM 1 library BITLIB; 2 use BITLIB.bit_pack.all; 3 entity ROM9_17 is 4 port (A, B, C: in bit; F: out bit_vector(0 to 3)); 5 end entity; 6 architecture ROM of ROM9_17 is 7 type ROM8X4 is array (0 to 7) of bit_vector(0 to 3); 8 constant ROM1: ROM8X4 := ("1010", "1010", "0111","0101", "1100", "0001", "1111", "0101"); 9 signal index: Integer range 0 to 7; 10 begin 11 Index <= vec2int(A&B&C); -- A&B&C Is a 3-bit vector 12 -- vec2int is a function that converts this vector to an integer 13 F <= ROM1 (index); 14 -- this statement reads the output from the ROM 15 end ROM; VHDL Operators When parentheses are not used, operators in class 7 have the highest precedence and are applied first, followed by class 6, then class 5, etc. Section 10.6 (p. 301) Figure 10-13: VHDL Description of a ROM VHDL shift Operators The shift operators are used to shift or rotate a bit_vector. In the following examples, A is an 8- bit vector equal to “10010101”: Figure 10-14: Comparator for Integers Section 10.6 (p. 302) Packages and Libraries Packages and libraries provide a convenient way of referencing frequently used functions and components. A package consists of a p...
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