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Unformatted text preview: ‘W’, ‘L’, ‘H’, ‘-’
(We will only use the values ‘U’, ‘X’, ‘0’, ‘1’, and ‘Z’.)
Section 10.8 (p. 304) Figure 10-16: Tri-State Buffer If a std_logic signal is assigned two different values, VHDL
automatically calls a resolution function to determine outcome. Figure 10-17: Tri-State Buffers Driving a Bus Figure 10-18: Resolution Function for Two Signals Arithmetic Operations on Std_logic_vectors
The basic IEEE standards do not define arithmetic
operations for bit_vectors or std_logic_vectors. The package
IEEE.Std_logic_unsigned defines arithmetic operations on
std_logic_vectors. The arithmetic operators (+, −, and *) and
comparison operators (<, <=, =, /=, >=, >) defined in this
package treat std_logic_vectors as unsigned binary
numbers. These operators are referred to as overloaded
operations. This means that the compiler will automatically
use the proper definition of the operator depending on its
Figure 10-19: Figure 9-12: Integrated Circuit with VHDL Code for Binary Adder entity IC_pin is
port(IO_pin: inout std_logic);
architecture bi_dir of IC_pin is
port(input: in std_logic; output: out std_logic);
signal input, output, en: std_logic;
begin -- connections to bi-directional I/O pin
IO_pin <= output when en = '1' else 'Z';
input <= IO_pin;
IC1: IC port map (input, output);
end bi_dir; Bi-Directional Input/Output Pin
Fig 10-20: VHDL Code for Bi-Directional I/O Pin Compilation and Simulation of VHDL code
After describing a digital system in VHDL, simulation of the
VHDL code is important for two reasons. First, we need to
verify the VHDL code correctly implements the intended
design, and second, we need to verify that the design
meets its specifications.
Before the VHDL model of a digital system can be
simulated, the VHDL code must first be compiled.
Figure 10-21: Section 10.9 (p. 307) Figure 10-22: Simulation of VHDL Code Compilation, Simulation, and Synthesis of VHDL Code...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas.
- Spring '08