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Unformatted text preview: one-to-one to the
list of interface signals specified in the component
Section 10.3 (p. 295) Signals and Constants Examples Input and output signals for a module are declared in a
port. Signals internal to a module are declared at the start
of an architecture, before begin, and can be used only
within that architecture. Port signals have an associated
mode (usually in or out), but signals do not.
A signal used within an architecture must be declared
either in a port or in the declaration section of an
architecture, but it cannot be declared in both places. Section 10.4 (p. 297) Section 10.4 (p. 297) Pre-defined VHDL Types A common user-defined type is the enumeration type in
which all of the values are enumerated. For example, the
type state_type is (S0, S1, S2, S3, S4, S5);
signal state : state_type := S1;
define a signal called state which can have any one of the
values S0, S1, S2, S3, S4, or S5 and which is initialized to
S1. If no initialization is given, the default initialization is the
left most element in the enumeration list, S0 in this example.
If we declare the signal state as shown above, the following
assignment statement sets state to S3: Section 10.4 (p. 298) state <= S3; (a) Block diagram Arrays
In order to use an array in VHDL, we must first declare an
array type, and then declar an array object. For example, the
following declaration defines a one-dimensional array type
type SHORT_WORD is array (15 downto 0) of bit;
Now we can declare array objects of type SHORT_WORD:
signal DATA_WORD: SHORT_WORD;
signal ALT_WORD: SHORT_WORD :=...
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- Spring '08