Chapter 10 - VHDL Introduction-2x2(1)

The architecture body contains statements that

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ions section, we can declare signals and components that are used within the architecture. The architecture body contains statements that describe the operation of the module. entity FullAdder is port (X,Y,Cin: in bit; --Inputs Cout, Sum: out bit); --Outputs end FullAdder; architecture Equations of FullAdder is begin -- concurrent assignment statements Sum <= X xor Y xor Cin after 10 ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equations ; Figure 10-10: Full Adder Module Figure 10-11: 4-Bit Binary Adder Fig 10-12: Simulation All of the simulation examples in this text use the ModelSim simulator from Model Tech. We will use the following simulator commands to test Adder4: Section 10.3 (p. 295) Structural Description of a 4-Bit Adder We have chosen to run the simulation for 50 ns because this is more than enough time for the carry to propagate through all of the full adders. The simulation results for the previous command list are: Components used within the architecture are declared at the beginning of the architecture using a component declaration of the form: component component-name port (list-of-interface-signals-and-their-types); end component; The connections to each component used in a circuit are specified by using a component instantiation statement of the form: label: component-name port map (list-of-actual-signals); Section 10.3, p. 296 Signals and Constants The list of actual signals must correspond...
View Full Document

Ask a homework question - tutors are online