Chapter 10 - VHDL Introduction-2x2(1)

# The keyword transport is required otherwise the

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Unformatted text preview: part are filtered out and do not appear at the output. The keyword transport is required; otherwise, the default inertial delay is assumed. Section 10.1 (p. 289) Z1 <= transport X after 10 ns; Z2 <= X after 10 ns; -- inertial delay 0 10 20 30 40 50 Figure 10-5: 2-to-1 Multiplexer This statement executes whenever A, I0, or I1 changes. Conditional Signal Assignments The general form of a conditional signal assignment statement is signal_name <= expression1 when condition1 else expression2 when condition2 [else expressionN]; This concurrent statement is executed whenever a change occurs in one of the expressions or conditions. If condition1 is true, signal_name is set equal to the value of expression2, etc. The line in square brackets is optional. Figure 10-6: Cascaded 2-to-1 MUXes The logic equation for a 4-to-1 MUX is F = A′B′I0 + A′BI1 + AB′I2 + ABI3 Here is a third way to model the MUX using a selected signal assignment statement. Thus, one way to model the MUX is with the VHDL statement F <= (not A and not B and I0) or (not A and B and I1) or (A and not B and I2) or (A and B and I3); Another way to model the 4-to-1 MUX is to use a conditional assignment statement: F <= I0 when A&B = “00” else I1 when A&B = “01” else I2 when A&B = “10” else I3; Figure 10-7: 4to-1 Multiplexer Figure 10-7: 4-to-1 Multiplexer VHDL Modules The general form of a selected signal assignment statement is with expression_s select signal_s <...
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## This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas.

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