Chapter 10 - VHDL Introduction-2x2(1)

This statement allows your design to access the

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Unformatted text preview: ackage declaration and an optional package body. A package declaration has the form: To access components and functions within a package requires a library statement and a use statement. This statement allows your design to access the BITLIB: library BITLIB; This statement allows your design to use the entire bit_pack package: use BITLIB.bit_pack.all; A package body has the form: This statement allows your design to use just the Nor2 component: use BITLIB.bit_pack.Nor2; Examples: bit_pack source, bit_pack_synth source (removes delay constructs) Package declaration for bit_pack includes component declaration component Nor2 port (A1, A2: in bit; Z: out bit); end component; The NOR gate is modeled using a concurrent statement. The entity-architecture for this component is -- two-input NOR gate entity Nor2 is port (A1, A2: in bit; Z: out bit); end Nor2; architecture concur of Nor2 is begin Z <= not(A1 or A2) after 10 ns; end concur; Figure 10-15: NOR-NOR Circuit and Structural VHDL Code Using Library Components IEEE Standard Logic Use of two-valued logic (bits and bit vectors) is generally not adequate for simulation of digital systems. In addition to ‘0’ and ‘1’, values of ‘Z’ (high-impedance or no connection), ‘X’ (unknown), and ‘U’ (uninitialized) are frequently used in digital system simulation. The IEEE standard 1164 defines a std_logic type that actually has nine values: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’,...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas.

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