Chapter 20 - VHDL for Digital System Design-2x2(1)

# 0 then sh 1 nextstate 1 37 else sh 1 nextstate

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 23 process (St, State, K, M) 24 begin 25 Load &lt;= '0'; Sh &lt;='0'; Ad &lt;='0'; Done &lt;='0'; -- control signals are '0' by default 26 case State is 27 when 0 =&gt; 28 if St = '1' then Load &lt;= '1'; NextState &lt;= 1; 29 else NextState &lt;= 0; end if; 30 when 1 =&gt; 31 if M = '1' then Ad &lt;= '1'; NextState &lt;= 2; 32 else if K = '0' then Sh &lt;= '1'; NextState &lt;= 1; 33 else Sh &lt;= '1'; NextState &lt;= 3; end if; 34 end if; 35 when 2 =&gt; 36 if K = '0' then Sh &lt;= '1'; NextState &lt;= 1; 37 else Sh &lt;= '1'; NextState &lt;= 3; end if; 38 when 3 =&gt; 39 Done &lt;='1'; NextState &lt;= 0; 40 end case; 41 end process; Figure 20-9b. VHDL Code for Multiplier with Shift Counter Figure 20-9c. VHDL Code for Multiplier with Shift Counter 42 process (clk) 43 begin 44 if clk'event and clk = '1' then 45 if load = '1' then 46 A &lt;= &quot;000000000&quot;; Count &lt;= &quot;000&quot;; -- clear A and counter 47 B &lt;= Mplier; 48 end if; -- load multiplier 49 if Ad = '1' then A &lt;= addout; end if; 50 if Sh = '1' then A &lt;= '0' &amp; A(8 downto 1); B &lt;= A(0)&amp; B(7...
View Full Document

Ask a homework question - tutors are online