Chapter 20 - VHDL for Digital System Design-2x2(1)

0 then sh 1 nextstate 1 37 else sh 1 nextstate

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Unformatted text preview: 23 process (St, State, K, M) 24 begin 25 Load <= '0'; Sh <='0'; Ad <='0'; Done <='0'; -- control signals are '0' by default 26 case State is 27 when 0 => 28 if St = '1' then Load <= '1'; NextState <= 1; 29 else NextState <= 0; end if; 30 when 1 => 31 if M = '1' then Ad <= '1'; NextState <= 2; 32 else if K = '0' then Sh <= '1'; NextState <= 1; 33 else Sh <= '1'; NextState <= 3; end if; 34 end if; 35 when 2 => 36 if K = '0' then Sh <= '1'; NextState <= 1; 37 else Sh <= '1'; NextState <= 3; end if; 38 when 3 => 39 Done <='1'; NextState <= 0; 40 end case; 41 end process; Figure 20-9b. VHDL Code for Multiplier with Shift Counter Figure 20-9c. VHDL Code for Multiplier with Shift Counter 42 process (clk) 43 begin 44 if clk'event and clk = '1' then 45 if load = '1' then 46 A <= "000000000"; Count <= "000"; -- clear A and counter 47 B <= Mplier; 48 end if; -- load multiplier 49 if Ad = '1' then A <= addout; end if; 50 if Sh = '1' then A <= '0' & A(8 downto 1); B <= A(0)& B(7...
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