Chapter 20 - VHDL for Digital System Design-2x2(1)

Behavioral vhdl code for multiplier of figure 18 6

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Unformatted text preview: C(3 downto 0) <= Mplier; --load the multiplier State <= 1; end if; Figure 20-2b. Behavioral VHDL Code for Multiplier of Figure 18-6 when 1 | 3 | 5 | 7 => --"add/shift" State if M = '1' then --Add multiplicand to ACC ACC(8 downto 4) <= ('0'& ACC(7 downto 4)) + Mcand; State <= State+1; else ACC <= '0' & ACC(8 downto 1); --Shift acc. right State <= State + 2; end if; when 2 | 4 | 6 | 8 => --"shift" State ACC <= '0' & ACC(8 downto 1); --Right shift State <= State + 1; when 9 => --end of cycle State <= 0; end case; end if; end process; Done <= '1' when State = 9 else '0'; end behave1; Figure 20-2c. Behavioral VHDL Code for Multiplier of Figure 18-6 Binary Multiplier Testing Test multiplier by creating command file and checking simulation results: -- command file to test multiplier view list add list CLK St State ACC done product force st 1 2, 0 22 force clk 1 0, 0 10 -repeat 20 force Mcand 1101 force Mplier 1011 run 200 Figure 20-3a. Command File for (13 by 11) Binary Multiplier Test Bench Need to run additional tests, esp. sp...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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