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Chapter 20 - VHDL for Digital System Design-2x2(1)

Chapter 20 - VHDL for Digital System Design-2x2(1) - Serial...

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(-&5659:99*787 %# ;<;;-)12 +45787 )./,./9:99&12 898>?>>8989:99*23 )*898./,34 Click the mouse to move to the next page± Use the ESC key to exit this chapter± ±²³´ 9+'/ &TIJ KTW F 6JWNFQ $IIJW ±²³± 9+'/ &TIJ KTW F %NSFW^ 0ZQYNUQNJW ±²³µ 9+'/ &TIJ KTW F %NSFW^ 'N[NIJW ±²³¶ 9+'/ &TIJ KTW F 'NHJ *FRJ 6NRZQFYTW ±²³· &TSHQZINSL 5JRFWPX Serial $dder with $ccumulator Section ±²³´ µp³ ¶·²¸ Figure !(8±!*: Block Diagram for Serial Adder with Accumulator )igure ±²¹´a³ V+'/ &ode for )igure ´º¹´ library ,((( use ,(((³67'D/2*,&D´´¸¶³ all entity XJWNFQ is 3ort ¹6Y º in XYIDQTLNH &QP º in XYIDQTLNH ;TZYº out XYIDQTLNHD[JHYTW¹µ downto ²»» end XJWNFQ architecture %JMF[NTWFQ of XJWNFQ is signal ;¼ <º XYIDQTLNHD[JHYTW¹µ downto ²» signal 6Mº XYIDQTLNH signal &N¼ &NUQZX º XYIDQTLNH signal 6ZRNº XYIDQTLNH signal 6YFYJ¼ 1J]Y6YFYJ º NSYJLJW range ² to µ ½½ ¶ XYFYJX )igure ±²¹´b³ V+'/ &ode for )igure ´º¹´ begin ;TZY !" ; ½½ KZQQ FIIJW JVZFYNTSX 6ZRN !" ;¹²» xor <¹²» xor &N &NUQZX !" ¹&N and ;¹²»» or ¹&N and <¹²»» or ¹;¹²» and <¹²»» ½½ UWTHJXX IJKNSJX HTRGNSFYNTSFQ QTLNH IWNHNSL 6M¼ 1J]Y6YFYJ process ¹6YFYJ¼ 6Y» begin case 6YFYJ is when ² "! if 6Y " ¾´·¶ then 6M !" ¾´¾ 1J]Y6YFYJ !" ´ else 6M !" ¾²¾ 1J]Y6YFYJ !" ² end if when ´ "! 6M !" ¾´¾ 1J]Y6YFYJ !" ± when ± "! 6M !" ¾´¾ 1J]Y6YFYJ !" µ when µ "! 6M !" ¾´¾ 1J]Y6YFYJ !" ² end case end process
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)igure ±²¹´c³ V+'/ &ode for )igure ´º¹´ process ¹HQP» begin if HQP¾J[JSY and HQP " ¾²¾ then 6YFYJ !" 1J]YXYFYJ ½½ ZUIFYJ XYFYJ WJLNXYJW if 6M " ¾´¾ then ; !" 6ZRN ¿ ;¹µ downto ´» ½½ XMNKY 6ZRN NSYT ; WJLNXYJW < !" < ¹²» ¿ <¹µ downto ´» ½½ WTYFYJ WNLMY < WJLNXYJW &N !" &NUQZX end if ½½ XYTWJ SJ]Y HFWW^ end if end process end %JMF[NTWFQ Sequential 0ultiplier Figure !(8±'7*: Block Diagram for Parallel Binary Multiplier )igure ±²¹±a³ %ehavioral V+'/ &ode for 0ultiplier of )igure ´º¹¶ library ,((( use ,(((³67'D/2*,&D´´¸¶³ $// use ,(((³67'D/2*,&D$5,7+³ $// use ,(((³67'D/2*,&D816,*1('³ $// entity RZQY¶;¶ is port ¹&QP¼ 6Yº in XYIDQTLNH 0UQNJW¼0HFSI º in XYIDQTLNHD[JHYTW¹µ downto ²» 'TSJº out XYIDQTLNH 3WTIZHYº out XYIDQTLNHD[JHYTW ¹À downto ²»» end RZQY¶;¶ )igure ±²¹±b³ %ehavioral V+'/ &ode for 0ultiplier of )igure ´º¹¶ architecture GJMF[J´ of RZQY¶;¶ is signal 6YFYJº NSYJLJW range ² to Á signal $&&º XYIDQTLNHD[JHYTW¹Â downto ²» ½½FHHZRZQFYTW alias 0º XYIDQTLNH is $&&¹²» ½½0 NX GNY ² TK $&& begin 3WTIZHY !" $&& ¹À downto ²» process ¹&QP» begin if &QP¾J[JSY and &QP " ¾´¾ then ½½J]JHZYJ TS WNXNSL JILJ TK HQTHP case 6YFYJ is when ²"! ½½NSNYNFQ 6YFYJ if 6Y"¾´¾ then $&&¹Â downto ¶» !" ò²²²²Ã ½½HQJFW ZUUJW $&& $&&¹µ downto ²» !" 0UQNJW ½½QTFI YMJ RZQYNUQNJW 6YFYJ !" ´ end if
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)igure ±²¹±c³ %ehavioral V+'/ &ode for 0ultiplier of )igure ´º¹¶ when ´ _ µ _ · _ À "! ½½ÃFIIÄXMNKYà 6YFYJ if 0 " ¾´¾ then ½½$II RZQYNUQNHFSI YT $&& $&&¹Â downto ¶» !" ¹¾²¾¿ $&&¹À downto ¶»» Å 0HFSI 6YFYJ !" 6YFYJÅ´ else $&& !" ¾²¾ ¿ $&&¹Â downto ´» ½½6MNKY FHH³ WNLMY 6YFYJ !" 6YFYJ Å ± end if when ± _ ¶ _ ¸ _  "! ½½ÃXMNKYà 6YFYJ $&& !" ¾²¾ ¿ $&&¹Â downto ´» ½½5NLMY XMNKY 6YFYJ !" 6YFYJ Å ´ when Á "! ½½JSI TK H^HQJ
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