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Chapter 20 - VHDL for Digital System Design-2x2(1)

Chapter 20 - VHDL for Digital System Design-2x2(1) - Serial...

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(-&59*7 %# ;-)2 +±7 )/,/9&2 8>89*3 )*8/,4 Click the mouse to move to the next page± Use the ESC key to exit this chapter± ±²³´ 9+'/ &TIJ KTW F 6JWNFQ $IIJW ±²³± 9+'/ &TIJ KTW F %NSFW^ 0ZQYNUQNJW ±²³µ 9+'/ &TIJ KTW F %NSFW^ 'N[NIJW ±²³¶ 9+'/ &TIJ KTW F 'NHJ *FRJ 6NRZQFYTW ±²³· &TSHQZINSL 5JRFWPX Serial $dder with $ccumulator Section ±²³´ µp³ ¶·²¸ Figure !8±!: Block Diagram for Serial Adder with Accumulator )igure ±²¹´a³ V+'/ &ode for )igure ´º¹´ library ,((( use ,(((³67'D/2*,&D´´¸¶³ all entity XJWNFQ is 3ort ¹6Y º in XYIDQTLNH &QP º in XYIDQTLNH ;TZYº out XYIDQTLNHD[JHYTW¹µ downto ²»» end XJWNFQ architecture %JMF[NTWFQ of XJWNFQ is signal ;¼ <º XYIDQTLNHD[JHYTW¹µ downto ²» signal 6Mº XYIDQTLNH signal &N¼ &NUQZX º XYIDQTLNH signal 6ZRNº XYIDQTLNH signal 6YFYJ¼ 1J]Y6YFYJ º NSYJLJW range ² to µ ½½ ¶ XYFYJX )igure ±²¹´b³ V+'/ &ode for )igure ´º¹´ begin ;TZY !" ; ½½ KZQQ FIIJW JVZFYNTSX 6ZRN !" ;¹²» xor <¹²» xor &N &NUQZX !" ¹&N and ;¹²»» or ¹&N and <¹²»» or ¹;¹²» and <¹²»» ½½ UWTHJXX IJKNSJX HTRGNSFYNTSFQ QTLNH IWNHNSL 6M¼ 1J]Y6YFYJ process ¹6YFYJ¼ 6Y» begin case 6YFYJ is when ² "¾ if 6Y " ¿´À then 6M !" ¿´¿ 1J]Y6YFYJ !" ´ else 6M !" ¿²¿ 1J]Y6YFYJ !" ² end if when ´ "¾ 6M !" ¿´¿ 1J]Y6YFYJ !" ± when ± "¾ 6M !" ¿´¿ 1J]Y6YFYJ !" µ when µ "¾ 6M !" ¿´¿ 1J]Y6YFYJ !" ² end case end process
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)igure ±²³´cµ V+'/ &ode for )igure ´¶³´ process ±HQP² begin if HQP³J[JSY and HQP " ³´³ then 6YFYJ !" 1J]YXYFYJ µµ ZUIFYJ XYFYJ WJLNXYJW if 6M " ³¶³ then ; !" 6ZRN · ;±¸ downto ¶² µµ XMNKY 6ZRN NSYT ; WJLNXYJW < !" < ±´² · <±¸ downto ¶² µµ WTYFYJ WNLMY < WJLNXYJW &N !" &NUQZX end if µµ XYTWJ SJ]Y HFWW^ end if end process end %JMF[NTWFQ Sequential 0ultiplier Figure !8±7: Block Diagram for Parallel Binary Multiplier )igure ±²³±aµ %ehavioral V+'/ &ode for 0ultiplier of )igure ´¶³· library ,((( use ,(((¹67'D/2*,&D¶¶º»¹ $// use ,(((¹67'D/2*,&D$5,7+¹ $// use ,(((¹67'D/2*,&D816,*1('¹ $// entity RZQY»;» is port ±&QP¼ 6Y½ in XYIDQTLNH 0UQNJW¼0HFSI ½ in XYIDQTLNHD[JHYTW±¸ downto ´² 'TSJ½ out XYIDQTLNH 3WTIZHY½ out XYIDQTLNHD[JHYTW ±¾ downto ´²² end RZQY»;» )igure ±²³±bµ %ehavioral V+'/ &ode for 0ultiplier of )igure ´¶³· architecture GJMF[J¶ of RZQY»;» is signal 6YFYJ½ NSYJLJW range ´ to ¿ signal $&&½ XYIDQTLNHD[JHYTW±À downto ´² µµFHHZRZQFYTW alias 0½ XYIDQTLNH is $&&±´² µµ0 NX GNY ´ TK $&& begin 3WTIZHY !" $&& ±¾ downto ´² process ±&QP² begin if &QP³J[JSY and &QP " ³¶³ then µµJ]JHZYJ TS WNXNSL JILJ TK HQTHP case 6YFYJ is when ´"Á µµNSNYNFQ 6YFYJ if 6Y"³¶³ then $&&±À downto »² !" ´´´´´Â µµHQJFW ZUUJW $&& $&&±¸ downto ´² !" 0UQNJW µµQTFI YMJ RZQYNUQNJW 6YFYJ !" ¶ end if
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)igure ±²³±c´ %ehavioral V+'/ &ode for 0ultiplier of )igure µ¶³· when ± _ ² _ ³ _ ´ "! µµ¶FII·XMNKY¶ 6YFYJ if 0 " ¸±¸ then µµ$II RZQYNUQNHFSI YT $&& $&&¹º downto »¼ ½" ¹¸¾¸¿ $&&¹´ downto »¼¼ À 0HFSI 6YFYJ ½" 6YFYJÀ± else $&& ½" ¸¾¸ ¿ $&&¹º downto ±¼ µµ6MNKY FHHÁ WNLMY 6YFYJ ½" 6YFYJ À  end if when  _ » _ à _ º "! µµ¶XMNKY¶ 6YFYJ $&& ½" ¸¾¸ ¿ $&&¹º downto ±¼ µµ5NLMY XMNKY
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Chapter 20 - VHDL for Digital System Design-2x2(1) - Serial...

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