Chapter 20 - VHDL for Digital System Design-2x2(1)

Command file of multiplier binary multiplier now

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Unformatted text preview: test bench code. Option “-Notrigger Mplier Mcand product” together with “-Trigger done” causes output to be displayed only when Done signal changes. -- Command file to test multiplier view list add list -NOtrigger Mplier Mcand product -Trigger done run 1320 ns Figure 20-6a. Command File of Multiplier Binary Multiplier Now model the same multiplier using two processes. One process to represent combinational circuit, and another to update all registers on the clock edge. Control Signals Registers Figure 20-6b. Simulation of Multiplier (with interpreted annotations) 1 library IEEE; Figure 20-7a. Two2 use IEEE.STD_LOGIC_1164.all; 3 use IEEE.STD_LOGIC_ARITH.all; process VHDL 4 use IEEE.STD_LOGIC_UNSIGNED.all; Model for Multiplier 5 entity mult4X4 is 6 port (Clk, St: in std_logic; 7 Mplier,Mcand : in std_logic_vector(3 downto 0); 8 Product: out std_logic_vector (7 downto 0); 9 Done: out std_logic); 10 end mult4X4; 11 architecture control_signals of mult4X4 is 12 signal State, Nextstate: integer range 0 to 9; 13 signal ACC: std_logic_vector(8 downto 0); --accumulator 14 ali...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas.

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