Chapter 20 - VHDL for Digital System Design-2x2(1)

Figure 20 7c two process vhdl model for multiplier 1

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Unformatted text preview: tiplier 41 if Ad = '1' then ACC(8 downto 4) <= addout; end if; 42 if Sh = '1' then ACC <= '0' & ACC(8 downto 1); end if; 43 -- Shift accumulator right 43 State <= Nextstate; 44 end if; 45 end process; 46 end control_signals; Figure 20-7b. Two-process VHDL Model for Multiplier Next, we will write VHDL code for a binary multiplier that multiplies two 8-bit numbers to give a 16-bit product. Figure 20-7c. Two-process VHDL Model for Multiplier 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.all; 3 use IEEE.STD_LOGIC_ARITH.all; 4 use IEEE.STD_LOGIC_UNSIGNED.all; 5 entity mult8X8 is 6 Port (CLK, St: in std_logic; 7 Mplier, Mcand : in std_logic_vector(7 downto 0); 8 Done : out std_logic; 9 Product: out std_logic_vector(15 downto 0)); 10 end mult8X8; Figure 20-8: Block Diagram for 8 x 8 Binary Multiplier Figure 20-9a. VHDL Code for Multiplier with Shift Counter 11 architecture Behavioral of mult8X8 is 12 signal State, NextState: integer range 0 to 3; 13 signal count: std_logic_vector (2 downto 0):="000"; -- 3-bit counter 14 signal A: std_logic_vector (8 downto 0); -- accumulator 15 signal B: std_logic_vector (7 downto 0); 16 alias M: std_logic is B(0); -- M is bit 0 of B 17 signal addout: std_logic_vector (8 downto 0); 18 signal K, Load, Ad, Sh: std_logic; 19 begin 20 Product <= A(7 downto 0) & B; -- 16-bit product is in A and B 21 addout <= '0' & A(7 downto 0) + Mcand; -- adder output is 9 bits including carry 22 K <= '1' when count = 7 else '0';...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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