Chapter 20 - VHDL for Digital System Design-2x2(1)

In all cases the number of flip flops is minimum and

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Unformatted text preview: s; 44 end DiceBehave; Figure 20-12c VHDL Code for Dice Game Controller 1 entity Counter is 2 port(Clk, Roll: in bit; 3 Sum: out integer range 2 to 12); 4 end Counter; 5 architecture Count of Counter is 6 signal Cnt1,Cnt2: integer range 1 to 6 := 1; 7 begin 8 process (Clk) 9 begin 10 if Clk'event and Clk='1' then 11 if Roll='1' then 12 if Cnt1=6 then Cnt1 <= 1; else Cnt1 <= Cnt1+1; end if; 13 if Cnt1=6 then 14 if Cnt2=6 then Cnt2 <= 1; else Cnt2 <= Cnt2+1; end if; 15 end if; 16 end if; 17 end if; 18 end process; Figure 20-13 Counter 19 Sum <= Cnt1 + Cnt2; 20 end Count; Module for Dice Game Concluding Remarks Typical synthesis results for five VHDL code examples from this chapter when the optimize for...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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