Chapter 20 - VHDL for Digital System Design-2x2(1)

Nextstate 0 else nextstate 3 end if when 4 if rb

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Unformatted text preview: range 2 to 12; 9 signal Sp: bit; 10 begin 11 process(Rb, Reset, Sum, State) 12 begin 13 Sp <= '0'; Roll <= '0'; Win <= '0'; Lose <= '0'; Figure 19-11: Block Diagram for Dice Game 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 case State is when 0 => if Rb = '1' then Nextstate <= 1; else nextstate <= 0; end if; when 1 => if Rb = '1' then Roll <= '1'; Nextstate <= 1; elsif Sum = 7 or Sum = 11 then Nextstate <= 2; elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3; else Sp <= '1'; Nextstate <= 4; end if; when 2 => Win <= '1'; if Reset = '1' then Nextstate <= 0; else nextstate <= 2; end if; when 3 => Lose <= '1'; if Reset = '1' then Nextstate <= 0; else nextstate <= 3; end if; when 4 => if Rb = '1' then Nextstate <= 5; else nextstate <= 4; end if; Figure 20-12b VHDL Code for Dice Game Controller Figure 20-12a VHDL Code for Dice Game Controller 29 when 5 => 30 if Rb = '1' then Roll <= '1'; Nextstate <= 5; 31 elsif Sum = Point then Nextstate <= 2; 32 elsif Sum = 7 then Nextstate <= 3; 33 else Nextstate <= 4; 34 end if; 35 end case; 36 end process; 37 process(CLK) 38 begin 39 if CLK'event and CLK = '1' then 40 State <= Nextstate; 41 if Sp = '1' then Point <= Sum; end if; 42 end if; 43 end proces...
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