Chapter 20 - VHDL for Digital System Design-2x2(1)

Testbench for multiplier when loop is entered index

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Unformatted text preview: ("1011", "1101", "0001","1000", "1111", "1101"); 19 constant Mplierarr: arr := ("1101", "1011", "0001","1000", "1111","0000"); Figure 20-5a. Testbench for Multiplier When loop is entered, index is initialized to first value in range, and sequential statements in the loop are executed. 19 signal CLK: std_logic :='0'; 20 signal St, Done: std_logic; 21 signal Mplier, Mcand: std_logic_vector(3 downto 0); 22 signal Product: std_logic_vector(7 downto 0); 23 begin 24 mult1: mult4X4 port map(CLK, St, Mplier, Mcand, Product, Done); 25 CLK <= not CLK after 10 ns; -- clock has 20 ns period 26 process 27 begin 28 for i in 1 to N loop 29 Mcand <= Mcandarr(i); 30 Mplier <= Mplierarr(i); 31 St <= '1'; 32 wait until CLK = '1' and CLK'event; 33 St <= '0'; 34 wait until done = '1' ; 35 wait until CLK = '1' and CLK'event; 36 end loop; Figure 20-5b. 37 end process; 38 end test1; Testbench for Multiplier Command file for executing the...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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