Chapter 20 - VHDL for Digital System Design-2x2(1)

# Vhdl code for divider figure 20 11a vhdl code for

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Unformatted text preview: not Subout (4); 21 Remainder &lt;= Dividend (7 downto 4); 22 Quotient &lt;= Dividend (3 downto 0); 23 24 25 26 27 28 29 30 31 32 33 34 35 State_Graph: process (State, St, C) begin Load &lt;= '0'; Overflow &lt;='0'; Sh &lt;= '0'; Su &lt;= '0'; case State is when 0 =&gt; if (St = '1') then Load &lt;='1'; NextState &lt;= 1; else Nextstate &lt;= 0; end if; when 1 =&gt; if (C = '1') then Overflow &lt;='1'; NextState &lt;= 0; else Sh &lt;= '1'; NextState &lt;= 2; end if; when 2 | 3 | 4 =&gt; if (C = '1') then Su &lt;= '1'; NextState &lt;= State; else Sh &lt;= '1'; NextState &lt;= State + 1; end if; Figure 20-11b. VHDL Code for Divider Figure 20-11a. VHDL Code for Divider 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 when 5 =&gt; if (C = '1') then Su &lt;= '1'; end if; NextState &lt;= 0; end case; end process State_Graph; Update: process (CLK) begin if CLK'event and CLK = '1' then -- rising edge of CLK State &lt;= NextState; if Load = '1' then Dividend &lt;= '0' &amp; Dividend_in; end if; if Su = '1' then Dividend(8 downto 4) &lt;= Subout; Dividend(0) &lt;= '1'; end if; if Sh = '1' then Dividend &lt;= Dividend (7 downto 0) &amp; '0'; end if; end if; end process update; end Behavioral; Figure 20-11c. VHDL Code for Divider Dice Game Simulator 1 entity DiceGame is 2 port (Rb, Reset, CLK: in bit; 3 Sum: in integer range 2 to 12; 4 Roll, Win, Lose: out bit); 5 end DiceGame; 6 architecture DiceBehave of DiceGame is 7 signal State, Nextstate: integer range 0 to 5; 8 signal Point: integer...
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## This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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