Chapter 20 - VHDL for Digital System Design-2x2(1)

Vhdl code for figure 18 1 sequential multiplier

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Unformatted text preview: e <= 0; end case; end process; Figure 20-1b. VHDL Code for Figure 18-1 Sequential Multiplier process (clk) begin if clk'event and clk = '0' then State <= Nextstate; -- update state register if Sh = '1' then X <= Sumi & X(3 downto 1); -- shift Sumi into X register Y <= Y (0) & Y(3 downto 1); -- rotate right Y register Ci <= Ciplus; end if; -- store next carry end if; end process; end Behavioral; Figure 20-1c. VHDL Code for Figure 18-1 Figure 18-7: Block Diagram for Parallel Binary Multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mult4X4 is port (Clk, St: in std_logic; Mplier,Mcand : in std_logic_vector(3 downto 0); Done: out std_logic; Product: out std_logic_vector (7 downto 0)); end mult4X4; Figure 20-2a. Behavioral VHDL Code for Multiplier of Figure 18-6 architecture behave1 of mult4X4 is signal State: integer range 0 to 9; signal ACC: std_logic_vector(8 downto 0); --accumulator alias M: std_logic is ACC(0); --M is bit 0 of ACC begin Product <= ACC (7 downto 0); process (Clk) begin if Clk'event and Clk = '1' then --execute on rising edge of clock case State is when 0=> --initial State if St='1' then ACC(8 downto 4) <= "00000"; --clear upper ACC AC...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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