Chapter 20 - VHDL for Digital System Design-2x2(1)

Write vhdl code to test multiplier by supplying

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Unformatted text preview: ecial cases and limiting cases. Test values for both the multiplicand and multiplier should include 0, maximum values, and smallest nonzero values. Write VHDL code to test multiplier by supplying sequence of values for the multiplicand and multiplier. VHDL code that is written to test another VHDL module is often referred to as a test bench. Figure 20-3b. Simulation Results for (13 by 11) Section 20.2 (p. 655) Use a for loop within the test bench code. Syntax for a VHDL for loop statement is [loop-label:] for index in range loop sequential statements end loop [loop-label]; Index is integer variable defined only within the loop. Variable must not be explicitly declared; it is automatically declared by the compiler. Figure 20-4: Test Bench for Multiplier 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 entity testmult is 6 end testmult; 7 architecture test1 of testmult is 8 component mult4X4 9 port (Clk: in std_logic; 10 St: in std_logic; 11 Mplier,Mcand : in std_logic_vector(3 downto 0); 12 Product: out std_logic_vector (7 downto 0); 13 Done: out std_logic); 14 end component; 15 constant N: integer := 6; 16 type arr is array(1 to N) of std_logic_vector(3 downto 0); 18 Mcandarr: arr :=...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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