Chapter 20 - VHDL for Digital System Design-2x2(1)

Stdlogicunsigned package 20 processstate st m 21

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Unformatted text preview: as M: std_logic is ACC(0); --M is bit 0 of ACC 15 signal addout: std_logic_vector(4 downto 0); -- adder o/p incl. carry 16 signal Load, Ad, Sh: std_logic; 17 Begin 18 Product <= ACC (7 downto 0); 19 addout <= ('0' & ACC(7 downto 4)) + Mcand; -- uses "+" operator from the ieee._std_logic_unsigned package 20 process(State, St, M) 21 begin 22 Load <='0'; Ad<='0'; Sh <='0'; Done <='0'; 23 case State is 24 when 0=> 25 if St='1' then Load <='1'; Nextstate <= 1; 26 else Nextstate <= 0; end if; 27 when 1 | 3 | 5 | 7 => --"add/shift" State 28 if M = '1' then Ad <='1'; --Add multiplicand 29 Nextstate <= State + 1; 30 else Sh <='1'; Nextstate <= State + 2; end if; 31 when 2 | 4 | 6 | 8 => --"shift" State 32 Sh <='1'; Nextstate <= State + 1; 33 when 9 => Done <= '1'; Nextstate <= 0; 34 end case; 35 end process; 36 process (CLK) -–Register update process 37 begin 38 if Clk'event and Clk = '1' then --executes on rising edge of clock 39 if Load = '1' then ACC(8 downto 4) <= "00000"; 40 ACC(3 downto 0) <= Mplier; end if; --load the mul...
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This document was uploaded on 03/16/2014 for the course EE 316 at University of Texas at Austin.

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