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Instructions add etc operate on registers only cannot

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Unformatted text preview: MW 0 1 Mux D cs420: speed with complexity MD 5 The load ­store architecture •  The processor includes a small number of “registers”  ­ ­ ­ think of them as fast memory locations, with dedicated paths to ALU •  All ALU instructions (ADD, etc.) operate on registers only (cannot mention memory locations) •  Only way to use memory is via: –  Load Ri, x // copy content of memory location x to Ri –  Store Ri, x // copy contents of Ri to memory location x •  Among other reasons, this is useful because specifying memory locations require many bits (32, 64) making instructions large cs420: speed with complexity 6 Condi3onal •  Instruction that examine a register, or the result of an arithmetic operation and set program counter (PC) to something other than the normal “next location” –  Otherwise, after every instruction, PC is incremented so as to execute the next instruction cs420: speed with complexity 7 Transla3ng the C if ­then statement •  We can use branch instructions to translate high ­level conditional statements into assembly code. R1 = *X; if (R1 < 0) R1 = -R1; R3 = R1 + R1; L LD R1, (X) BNN R1, L LD R2,#0 SUB R1, R2, R1 ADD R3, R1, R1 // R1 = *X // Skip negation if R1 is not negative // R1 = 0-R1 // R3 = R1 + R1 •  Sometimes it s easier to invert the original condition. Here, we effectively changed the R1 < 0 test into R1 >= 0. cs420: speed with complexity 8 Transla3ng the C for loop •  Here is a translation of the for loop, assuming a “BGT” “Branch if greater than” instruction R1 = 0; for (R2 = 1; R2 <= 5; R2++) R1 = R1 + R2; R3 = R1 + R1; FOR L LD LD BGT ADD ADD JMP ADD R1, R2, R2, R1, R2, FOR R3,...
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