3 computer architecture and design inlab 7 4 priority

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Unformatted text preview: here, so the assignment "state <= nextstate" will produce unpredictable results. 3 Computer Architecture and Design, InLab 7 4. Priority Encoder module p r i o r i t y ( input output always @( ∗ ) if (a [3]) else i f ( a [ 2 ] ) else i f ( a [ 1 ] ) else i f ( a [ 0 ] ) endmodule [3:0] a, reg [ 3 : 0 ] y ) ; y y y y = = = = 4 ’ b1000 ; 4 ’ b0100 ; 4 ’ b0010 ; 4 ’ b0001 ; there should be a "begin" statement after "always @ (*)" and an end statement before "endmodule" 5. And gate with three inputs module and3 ( input a, b, c , output reg y ) ; reg tmp ; always @ ( a , b , c ) begin tmp <= a & b ; y <= tmp & c ; end endmodule the two assignment statements should use blocking assignments as opposed to non-blocking assignments because the second statements depends on the first statement already being executed. 4 Computer Architecture and Design, InLab 7 5 6. Register module f l o p r s ( input input input input [3:0] output reg [ 3 : 0 ] clk , reset , set , d, q); always @( posedge c l k , posedge r e s e t ) if ( reset ) q <= 0 ; else q <= d ; always @ ( s e t ) i f ( s e t ) q <=1; endmodule The two always block conflict each other because they both are assigning to q. The "if (set) q<=1;" should be moved directly after the first if statement in the first always block. 4 Lab overview In this Lab, you will use the Verilog hardware description language to implement and verify a 32 bit sign extender module and a register file. Note: the modules that you implement in this lab and several following labs will be used in building a complete single cycle processor. So it is advised to implement and test your models properly. 5 32 bit sign extender A 32 bit extender takes as...
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