If the control bit is 1 then the value is zero

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Unformatted text preview: input a 16-bit immediate value and based on the control bit that is passed as input, the value is either zero extended or sign extended to a 32 bit value. If the control bit is 1 then the value is zero extended otherwise it is sign extended. Write a Verilog module to test the following extender module. module S i g n E x t e n d e r (BusImm , Imm16 , C t r l ) ; output [ 3 1 : 0 ] BusImm ; input [ 1 5 : 0 ] Imm16 ; input C t r l ; wire e x t B i t = ( C t r l ? 0 : Imm16 [ 0 ] ) ; assign BusImm = {{ 16 { e x t B i t } } , Imm16 } ; endmodule Computer Architecture and Design, InLab 7 6 BusImm is the 32-bit output, Imm16 is the 16 bit input, and Ctrl is a 1 bit input control signal. Implement a testbench for module extender. Test the module with the testbench using Xilinx ISE. The module does contain a mistake, find it using you test module and correct it. Run the synthesize tool to make sure that the extender module can be translated into logic. 6 Register File Implement a 32x32 register file. You may use behavioral style Verilog programming, but your code must be synthesizable. Run the synthesize tool to make sure your Verilog code can be translated into logic. The register file contains 32, 32-bit registers. The file MiniRegisterFile.v contains a small register file which is missing several features, but can provide a starting point. Below is a specification of the register file; • Buses A, B, and W are 32 bit wide. • When RegWr is set to 1, then the data on Bus W is stored in the register specified by Rw, at negative clock edge. • Register 0 must always read zero. • Data from registers (as specified by Ra and Rb) is sent on Bus A and Bus B respectively, at the positive edge of the clock. • The Reg...
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This lab report was uploaded on 03/18/2014 for the course ECEN 350 taught by Professor Sprintston during the Spring '09 term at Texas A&M.

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