V testbench write a testbench to test your code for

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Unformatted text preview: ister File module should have the following interface. module R e g i s t e r F i l e ( BusA , BusB , BusW, RA, RB, RW, RegWr , Clk ) ; • Test your code against the provided RegisterFileTest.v testbench. Write a testbench to test your code for the following inputs of Ra, Rb, Rw, BusW and RegWr. Initialize the register file to the following data. Register 0 1 2 3 4 5 6 7 Value 0x00000000 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 Register 8 9 10 11 12 13 14 15 Value 0x00000008 0x00000009 0x000000A 0x000000B 0x000000C 0x000000D 0x000000E 0x000000F Computer Architecture and Design, InLab 7 7 Bus A Ra Rb 32x32 Register File Rw Bus B Bus W Clk RegWr Fig. 1: Register File All the other registers should have a value of zero. Specify the values on BusA and BusB along with the registers (if any) that will be modified. Put N/A if none are modified: Ra Rb Rw RegWr Bus W 0 2 4 6 8 A C E 1 3 5 7 9 B D F 0 1 0 A B C D E 0 0 1 1 1 0 1 0 0x00000000 0x00001000 0x00001000 0x00001010 0x00103000 0x00000000 0x0000ABCD 0x09080009 Bus A Bus B Modified 0x00000000 0x00000001 N/A 0x00000002 0x00000003 N/A 0x00000004 0x00000005 N/A 0x00000006 0x00000007 10 0x00000008 0x00000009 11 0x0000000A 0x0000000B N/A 0x0000000C 0x0000ABCD 12 0x09080009 0x0000000F N/A...
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