25 pp 1379 1384 december 1990 eecs 240 lecture 7

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Unformatted text preview: ndwidth - ensure stability (nondominant pole at source of M2) Ref: Klaas Bult, Govert J. G. M. Geelen; A fast-settling CMOS Op amp for SC circuits with 90-dB DC gain, IEEE Journal of Solid-State Circuits, vol. 25, pp. 1379 - 1384, December 1990. EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 20 Noise Analysis EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 21 Noise Summary EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 22 Noise Detail Booster amplifier and cascode contribute noise at high frequency. Actual boosters have more transistors additional noise. Some noise might be filtered out by sampling switch. EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 23 Cascode Noise Noise from cascode often insignificant. Can contribute substantially at high frequency with lots of (capacitive) degeneration at the source of the cascode transistor (poor layout). EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 24 If it works, do it again! • Since in advanced scaled CMOS gmro is small, we can use nested gain boosting for higher output impedance. • Watch out for pole-zero doublets! EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 25 Matching • Systematic mismatch – ∆VDS – source resistance – gradients • Random mismatch – ∆ (W/L) – ∆VTH EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 26 Random Mismatch • Model: (we need an equation with W/L in it … resort to square-law) W I D1 = 1 µCox 2 L W I D 2 = 1 µCox 2 L 2 (VGS − VTH 1 ) 1 2 (VGS − VTH 2 ) 2 ∆I D = I D 1 − I D 2 • • Mismatch: ∆ID, ∆(W/L), ∆VTH Substitute: W W W ∆ = − L L 1 L 2 W L ∆VTH = VTH 1 − VTH 2 • I D = 0.5(I D1 + I D 2 ) VTH = 0.5(VTH 1 + VTH 2 ) W W = 0. 5 + L 1 L 2 W ∆ ∆I D 2 ∆VTH L = − ID W VGS − VTH L choose large VGS-VTH (V*) EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 27 Mismatch Example • σ W ∆ L Represent mismatch as random quantities • Variances (squares!) add … like noise • Use large V* (or degeneration) for good current mirror matching = 1% W L σ ∆V = 3mV TH VGS − VTH = 300mV σ 2 ∆I D ID =σ + 2 W ∆ L W L 2 4σ ∆VTH (VGS − VTH )2 2 2 ×3 −6 = (0.01) + = (100 + 100 ) × 10 300 2 = (1.4% ) 2 EECS 240 Lecture 7: Current Sources © 2006 A. M. Niknejad and B. Boser 28 Yield • 0.6 0.451 0.8 0.576 1.0 0.683 0.766 1.4 0.838 1.6 0.890 0.928 0.954 2.2 0.972 2.4 0.984 2.6 0.991 0.995 3.0 EECS 240 Lecture 7: Current Sources 0.311 2.8 Typical design goal: ± 3σ (“6σ”), i.e. k=3 0.159 2.0 yield = 0.954 = 95.4% 0.2 1.8 E.g. need ±2.8% matching σ = 1.4%, k = 2.8 / 1.4 = 2 Yield 1.2 • Yield = fraction of good dies k 0.4 • 0.997 © 2006 A. M. Niknejad and B. Boser 29...
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This note was uploaded on 03/18/2014 for the course EECS 240 taught by Professor Boser during the Spring '04 term at University of California, Berkeley.

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