lect4 - EECS 240 Analog Integrated Circuits Lecture 4...

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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 1 EECS 240 EECS 240 A A nalog Integrated Circuits nalog Integrated Circuits Lecture 4: Small Lecture 4: Small - - Signal Models for Signal Models for Analog Design Analog Design Ali M. Niknejad and Bernhard E. Boser © 2006 Department of Electrical Engineering and Computer Sciences
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 2 MOSFET Models for Design MOSFET Models for Design SPICE (BSIM) For verification Device variations Hand analysis Square law model Small-signal model • Challenge Complexity / accuracy tradeoff How can we accurately design when large signal models suitable for hand analysis are off by 50% and more?
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 3 Device Variations Device Variations Run-to-run parameter variations: E.g. implant doses, layer thickness Affect V TH , µ , C ox , R ± , … How model in SPICE? Nominal / slow / fast parameters E.g. fast: low V TH , high µ , high C ox , low R ± Combine with supply extremes Pessimistic but numerically tractable Æ improves chances for working Silicon
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 4 Threshold Voltage V Threshold Voltage V TH TH Strong function of L Use long channel for V TH matching Process variations – Run-to-run How characterize? – Slow/nominal/fast Both worst-case & optimistic
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 5 V V TH TH Design Considerations Design Considerations Approximate Values (L = 0.5 µ m) V THN = 600mV γ n =0.5 rt-V V THP = -700mV γ p =0.4 rt-V Back-Gate Bias e.g. V SB = 400mV Æ V THN = 110mV Variations: Run-to-run: +/- 50mV (very process dependent) – Device-to-device: σ = 2mV (L > 1 µ m, common-centroid) Use insensitive designs diff pairs, current mirrors Æ value of V TH unimportant (if < V DD )
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 6 Device Parameters for Design Device Parameters for Design Region: moderate or strong inversion / saturation Most common region of operation in analog circuits XTR behaves like transconductor: voltage controlled current source Key design parameters Large signal Current I D Æ power dissipation Minimum V DS Æ available signal swing Small signal Transconductance g m Æ speed / voltage gain Capacitances C GS , C GD , … Æ speed Output impedance r o Æ voltage gain
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 7 Low Frequency Model Low Frequency Model A Taylor series expansion of small signal current gives (neglect higher order derivatives) Square law model:
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 8 Transconductance Transconductance Using the square law model we have three equivalent forms for g m in saturation
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 9 Weak Weak Invesion Invesion g g m m In weak inversion we have bipolar behavior
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