ECE3060 hw8 - ECE3060: VLSI and Advanced Digital Design...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE3060: VLSI and Advanced Digital Design Fall 2004 Homework #8: due Nov. 29 6:45PM 1. Consider following network with inputs { a,b,c,d,e } and outputs { x,y,z }. (Show all your work to receive the full credit.) x = abd + ade’ + ae + c’e y = ab + ac + ad + ae’ z = ae + be + bce’ + c’e a) Compute all kernels and co-kernels of x, y, and z . b) Perform the Extract operation between x and y and then x and z . Draw the corresponding network graph. c) Compute the gain of the Extract operation from part b) in terms of area and delay reduction (Hint: use the number of literals to compute area and the number of the longest path stages to compute delay). d) Is ae included in z ? (i.e., does z cover implicant ae ) Answer the question using an ROBDD variable order of ( a,b,c,d,e ). 2. Implement a T-gate based shifter that can shift to left up to 4 bits. Input and output ports of the shifter are as follows. You are given 4-bit data to shift (D[3:0]). However, you need to implement a shifter with an 8-bit input port by assigning the given data (D[3:0])
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This homework help was uploaded on 04/07/2008 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Tech.

Page1 / 2

ECE3060 hw8 - ECE3060: VLSI and Advanced Digital Design...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online