ECE3060 hw8_sol

# ECE3060 hw8_sol - ae is included in z 2(30pts I[7:0 =...

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ECE3060: VLSI and Advanced Digital Design Fall 2004 Homework #8: due Nov. 29 6:45PM 1. a) (10pts) Kernels Cokernels X bd+de’+e b+e’ a+c’ x a ad e 1 Y b+c+d+e’ a Z e+ce’ a+b+c’ z b e 1 b) (10pts) Let t = b+e’ , then we can extract t from x and y as follows, x = tad+ae+c’e, y = ta+ca+da Let w = a+c’ , then we can extract w from x and z as follows, x = we+abd+ade’=we+tad, z = we+be+bce’ Network graph c) (5pts) The number of literals decreases from 27 to 22. The number of the longest path stages (=delay) increases from 1 to 2.

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d) (15pts) ROBDD of z ae It is tautology. Therefore,

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Unformatted text preview: ae is included in z . 2. (30pts) I[7:0] = D[3:0]0000 3. a) (10pts) Inv AND2 NOR2 OAI21 b) (20pts) load node gate arrival time 2 4 5 7 1 INV 10 16 20 22 26 2 INV 5 11 15 17 21 3 INV 7 13 17 19 23 4 INV 3 9 13 15 19 5 AND2 20 28 32 34 38 NOR2 10 18 20 21 23 6 AND2 17 25 29 31 35 NOR2 7 15 17 18 20 7 INV 18 24 28 30 34 8 AND2 17 25 29 31 35 9 AND2 29 37 41 43 47 f INV 37 49 OAI21 35 49 Min delay =49, Now we have two choices. Choice 1: 1 OIA21, 1 AND2, 1 NOR2, Area=22 Choice 2: 2 Inv, 2 AND2s, 2 NOR2, Area=24 Therefore, the choice 1 has smaller area....
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## This homework help was uploaded on 04/07/2008 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Tech.

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ECE3060 hw8_sol - ae is included in z 2(30pts I[7:0 =...

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