Lab 5 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

Lab 5 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

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Lab 5 - FL13 Lab 5 assignment is due on Friday, September 27 in class. This lab is to be done in the EWS computer lab (DCL 440, DCL 520, etc.). Working on it remotely is not advisable as there are numerous technical difficulties in getting the software to work properly with remote access. Plan your time accordingly. Introduction to Mentor Graphics HDL Designer software The goal of this lab is to introduce you to industry design tools and simulation environments that can help you design, test, and debug your circuits quickly and efficiently. Getting Started 1. Open a new terminal. 2. Create a folder for your lab 5 assignment in your ece198jl directory. Name it ‘lab5’. Change to this folder. 3. Run HDL Designer by typing in hdl_designer & . 4. Since you are probably running this tool for the first time, HDL Setup Assistant Wizard window will pop up. Click on the Cancel button and wait until the dialog box disappears. You should see the following Design Manager window appearing on your screen. Creating a new HDL project 1. Inside HDL designer, create a new project. Select File->New->Project on the menu and answer Yes to the pop-up question about closing SCRATCH_LIB. You should see the following dialogue box. Name your project “lab5”, and change the Directory to /home/[your_netid]/ece198jl/lab5/ (or wherever you would like your lab to be stored). Click Next .
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2. The next screen will ask you to confirm the name of your project and the directory to store your project. Double check everything and click Next if everything is correct. 3. Choose the Open the project radio button and click Finish . 4. After you click Finish , you should see the following window for the Design Manager . The Design Manager will help you find all files that are part of your project and help you organize them.
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Creating new circuits In this section, we will show you how to create a new circuit. In particular, we will show you how to implement the XOR function by using AND gates, OR gates, and NOT gates. The XOR function has two inputs a and b and one output f . The XOR function can be thought of as an odd/even detector: f is 1 when there are an odd number of 1s in its inputs and 0 when there are an even number of 1s in its inputs. For example, the first row has zero 1s in the inputs, so the output is 0, but the second row has one 1 in the inputs, so the output is 1. The relationship between the inputs and outputs is formally defined by the truth table below where the inputs are listed in the two left columns and the output is in the column on the right. a b f = a XOR b 0 0 0 0 1 1 1 0 1 1 1 0 Create a new block diagram 1. In the design manager window, click the New/Add button on the top left. You should see the dialogue box below. Choose Graphical View in the left pane and Block Diagram in the right pane. Make sure that VHDL is selected and then click Next .
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2. Enter the name my_xor as your “design unit name” and then click Finish .
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Lab 5 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

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