Lab 5 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

You s hould notic e that wires c an be drawn only

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Unformatted text preview: ate the end point of y our s ignal. You s hould notic e that wires c an be drawn only with horiz ontal or vertic al c omponents and HDL Des igner will mak e its bes t gues s for where to put s ome 90 degree turns rather than mak e diagonal wires . As long as y ou don't c lic k Es c , eac h mous e pres s will either s tart a wire (if y ou are not c urrently drawing a wire), end a wire (if y ou c lic k on the port of another c omponent), or allow y ou to c hange the direc tion of y ou wire (if y ou c lic k in an empty s pac e). If y ou c lic k on an ex is ting s ignal, it will c reate a new wire that c arries the s ame s ignal to a different des tination. A blac k c irc le at an inters ec tion s hows that the two wires are c onnec ted and c arry the s ame s ignal. Inters ec tions without this blac k c irc le are not c onnec ted. 8. Add the remaining s ignals and wires s o that y our diagram res embles the figure below. 9. Change the name of y our s ignals . As y ou added wires that c onnec ted to the input and output ports , y ou may have notic ed that the input ports now have names by them that s ay “din” may be followed by a number and that the output port now has a name by it that s ay s “dout” may be followed by a number (the number will vary depending on the order y ou c reated y our s ignals ). Let's c hange thes e default names to matc h the truth table for the XOR func tion. a. Double c lic k the name of the top input port. You s hould s ee the tex t s imilar to “din : s td_logic ”. “din” is the name of y ou s ignal and “s td_logic ” tells us that the s ignal is a s tandard logic s ignal that c an have only the values of 0 or 1. Change the name of y our s ignal to “a” s o that the tex t now reads “a : s td_logic ”. Do NOT c hange the s td_logic part of the name. Note: y ou c an inc reas e the font s iz e by c lic k ing the A^ button in the top right. b. Change y our other variable names s o that y our c irc uit look s as s hown below. Notic e that the wires that branc h off y our original a and b s ignals are als o now labeled with the name of the s ignal. 10. Generate the HDL for y our c irc uit. In order for the s imulator to s imulate y our c irc uit, the s c hematic y ou drew needs to be c onverted into a language that the s imulator unders tands . The s imulator us es a language c alled a VHSIC Hardware Des c ription Language (VHDL). Clic k the HDL menu and s elec t Ge ne ra te VHDL configura tions. Choos e ove rw rite e x isting file s and c lic k Ge ne ra te then c lic k Ye s. A log window s hould s ay Generation c ompeted s uc c es s fully. If not, double c hec k all of y our wires to mak e s ure they are c onnec ted and try again. 11. Save and c los e the window. Simulating your circuit In this s ec tion, we will learn how to s imulate a c irc uit s o that we c an mak e s ure that it behaves as we ex pec t. Setup the Simulation 1. Start the s imulator a. In the Des ign Manager window, mak e s ure that m y...
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